• Electronics and Telecommunications Trends
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• v.13 no.3 s.51
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• pp.61-70
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• 1998

The obvious way to make a computer system more powerful is to make the processor as fast as possible. Furthermore, adopting a large number of such fast processors would be the next step. This multiprocessor system could be useful only if it distributes workload uniformly and if its processors are fully utilized. To achieve a higher processor utilization, memory access latency must be reduced as much as possible and even more the remaining latency must be hidden. The actual latency can be reduced by using fast logic and the effective latency can be reduced by using cache. This article discusses what the memory latency problem is, how serious it is by presenting analytical and simulation results, and existing techniques for coping with it; such as write-buffer, relaxed consistency model, multi-threading, data locality optimization, data forwarding, and data prefetching.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.10b
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• pp.1481-1484
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• 2001

Most implementations of HTTP servers do not distinguish among requests for hypermedia data from different clients. Commercialization of Web site is becoming increasingly common. Therefore providing quality of service with members paying to the site is often an important issue for the hosts. For some uses, such as web prefetching or multiple priority schemes, different levels of service are desirable. We propose server-side TCP connection management mechanisms to provide two different levels of Web service, high and regular levels by setting different timeout for inactive connection. Therefore this mechanism can effectively provide different service classes even in the absence of operating system and network support.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.4
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• pp.1655-1673
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• 2018

Mobile computing environment is subject to the constraints of bounded network bandwidth, frequently encountered disconnections, insufficient battery power, and system asymmetry. To meet these constraints and to gain high scalability, data broadcasting has been proposed on data transmission techniques. However, updates made to the database in any broadcast cycle are deferred to the next cycle in order to appear to mobile clients with lower data currency. The main goal of this paper is to enhance the transaction performance processing and database currency. The main approach involves decomposing the main broadcast cycle into a number of sub-cycles, where data items are broadcasted as they were originally sequenced in the main cycle while appearing in the most current versions. A concurrency control method AOCCRBSC is proposed to cope well with the cycle decomposition. The proposed method exploits predeclaration and adapts the AOCCRB method by customizing prefetching, back-off, and partial backward and forward validation techniques. As a result, more than one of the conflicting transactions is allowed to commit at the server in the same broadcast cycle which empowers the processing of both update and read-only transactions and improves data currency.

• Journal of the Semiconductor & Display Technology
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• v.22 no.2
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• pp.6-10
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• 2023

High-potential data can be predicted and stored in the cache to prevent cache misses, thus reducing the processor's request and wait times. As a result, the processor can work non-stop, hiding memory latency. By utilizing the temporal/spatial locality of memory access, the prefetcher introduced to improve the performance of these computers predicts the following memory address will be accessed. We propose a prefetcher that applies the GRU model, which is advantageous for handling time series data. Display the currently accessed address in binary and use it as training data to train the Gated Recurrent Unit model based on the difference (delta) between consecutive memory accesses. Finally, using a GRU model with learned memory access patterns, the proposed data prefetcher predicts the memory address to be accessed next. We have compared the model with the multi-layer perceptron, but our prefetcher showed better results than the Multi-Layer Perceptron.

• The KIPS Transactions:PartA
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• v.12A no.1 s.91
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• pp.41-52
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• 2005

Memory reference instruction caused by cache miss is the critical factor that limits the processing power of processor. Cache prefetching technique is an effective way to reduce the latency due to memory access. However, excessively aggressive prefetch leads to cache pollution and finally to cancel out the advantage of prefetch. In this study, an active prefetch filtering scheme is introduced which dynamically decides whether to commence prefetching after referring a filtering table to reduce the cache pollution due to unnecessary prefetches. For the precision filtering, an evicted address referencing scheme has been proposed where the filter directly compares the current prefetch address with previous unnecessary prefetch addresses stored in filtering table. Moreover, a small sized exclusive prefetch cache has been introduced to increase the amount of eviction of unnecessarily prefetched addresses to enhance the accuracy of dynamic filtering. The exclusive prefetch cache also prevents useful demand data from being pushed out by prefetched data, while the evicted address direct referencing scheme enables the prefetch cache to keep most of useful prefetch data within its small size. Experimental results from commonly used general and multimedia benchmarks show that the average cache miss ratio has been decreased by $13.3{\%}$ by virtue of enhanced filtering accuracy compared with conventional schemes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7B
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• pp.598-612
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• 2004

Client requests have increased with the improvement of network resources at client side, whereas network resources at server side could not keep pace with the increased client request. Therefore, it is primary factor of the Qos that efficiently utilize network resources at server side. In this paper, we proposed a new model that peer-to-peer transfer scheme for partial multimedia stream based on CIWP which it decrease server network bandwidth by utilizing client disk resources saves additional server network resources. Especially, adapting Threshold_Based Multicast scheme guarantees to do that data transfer within clients never exceed service time of previous peer by restriction of which data size transferring from previous peer less than data size transferring from server. Peer-to-peer transfer within clients is limited in same group classified as ISPs. Our analytical result shows that proposed scheme reduces appling network resources at server side as utilizing additional client disk resource. furthermore, we perform various simulation study demonstrating the performance gain through comparing delay time and proportion of waiting requesters. As a result, when we compared to Threshold_Based Multicast scheme, the proposed scheme reduces server network bandwidth by 35%.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.82-94
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• 2015

In this paper, we propose hardware prefetch mechanism with an efficient cache replacement policy by giving priority to the trigger block in which a spatial region and producing a spatial region by using the displacement field. It could be taken into account the sequence of the program since a history is based on the trigger block of history record, and it could be quickly prefetching the instructions or data address by adding a stored value to the trigger address and displacement field since a history is stored as a displacement value. Also, we proposed a method of replacing at random by the cache replacement policy from the low priority block when the cache area is full after giving priority to the trigger block. We analyzed using the memory simulator program gem5 and PARSEC benchmark to assess the performance of the hardware prefetcher. As a result, compared to the existing hardware prefecture to generate the spatial region using a bit vector, L1 data cache miss rate was reduced about 44.5% on average and an average of 26.1% of L1 instruction misses occur. In addition, IPC (Instruction Per Cycle) showed an improvement of about 23.7% on average.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.217-219
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• 2003

멀티미디어 응용 프로그램은 방대한 양의 데이터를 실시간으로 고속 처리해야 한다. 적재/저장과 같은 메모리 참조 명령어는 프로세서의 고속 수행에 방해가 되는 주요인이다. 본 논문에서는 메모리 참조 속도를 향상시키기 위해 멀티미디어 데이터의 주소간격이 규칙적으로 참조되는 특성을 활용하여 다음에 참조될 데이터를 미리 캐시로 선인출 함으로써 실행시 캐시 미스율을 줄이고 또한 전체 수행시간을 줄이는 효과적인 방법을 제안한다. 제안한 방법은 캐시 미스율을 줄이는 방법으로서 데이터 선인출 기법을 사용하는데 주소간격을 이동한 기존 연구들에 비해 캐시 미스율에 있어서 평균적으로 27%향상되었다.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.11a
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• pp.135-138
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• 2003

멀티미디어 응용프로그램은 처리데이터를 참조할 때 대부분 간격이 일정한 스트리밍 패턴으로 참조한다. 이 특성을 선인출 방법에 적용하여 멀티미디어 응용프로그램의 성능을 항상 시킬 수 있다. 이 논문에서는 하드웨어기반의 규칙 선인출 방법에서 참조예측표에 운영하는 방법을 제안한다. 크기가 제한되어 있는 참조예측표에 메모리 참조 명령어를 추가할 때 주소간격이 0인 행을 우선적으로 제거함으로써 비용절감의 효과를 가져올 수 있다. 실험 결과 제안한 방법과 기존의 참조예측표를 FIFO 방식으로 운영하는 방법을 비교할 때 제안한 방법의 경우 참조예측표의 크기를 반으로 줄여도 거의 같은 효과를 볼 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.23-28
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• 2017

Non-volatile RAM (NVRAM) provides many opportunities to improve the performance of computing devices. In this paper, we present an approach that reduces the user-perceived latency of browsers by using NVRAM. To this end, we first analyze the browser launch process, and then employ several techniques that improve the performance of each step by using NVRAM. Specially, we focus on minimizing the launch time of browser by 1) prefetching the block sequence required for browser launch, 2) caching the web resources in the fast NVRAM, and 3) reusing the displayed bitmap data in the frame buffer. Through implementation, we show that our scheme significantly reduces the launch time of browsers.