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http://dx.doi.org/10.5573/ieie.2015.52.10.082

Instructions and Data Prefetch Mechanism using Displacement History Buffer  

Jeong, Yong Su (Department of Electronic Engineering, Inha University)
Kim, JinHyuk (Department of Electronic Engineering, Inha University)
Cho, Tae Hwan (Department of Electronic Engineering, Inha University)
Choi, SangBang (Department of Electronic Engineering, Inha University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.52, no.10, 2015 , pp. 82-94 More about this Journal
Abstract
In this paper, we propose hardware prefetch mechanism with an efficient cache replacement policy by giving priority to the trigger block in which a spatial region and producing a spatial region by using the displacement field. It could be taken into account the sequence of the program since a history is based on the trigger block of history record, and it could be quickly prefetching the instructions or data address by adding a stored value to the trigger address and displacement field since a history is stored as a displacement value. Also, we proposed a method of replacing at random by the cache replacement policy from the low priority block when the cache area is full after giving priority to the trigger block. We analyzed using the memory simulator program gem5 and PARSEC benchmark to assess the performance of the hardware prefetcher. As a result, compared to the existing hardware prefecture to generate the spatial region using a bit vector, L1 data cache miss rate was reduced about 44.5% on average and an average of 26.1% of L1 instruction misses occur. In addition, IPC (Instruction Per Cycle) showed an improvement of about 23.7% on average.
Keywords
cache memory; prefetching; spatial correlation;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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