• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.1
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• pp.63-68
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• 2011

Many countries all over the world have been doing lunar exploration projects. Korea has also been doing basic research on lunar exploration. The development of communication systems for lunar exploration projects is one of the most important aspects of performing a successful lunar mission. In this paper, we design a DSP (Digital Signal Processor) prototype based on the requirement analysis of a communication link for lunar exploration and implement its core module considering the international standards for deep space communications to perform a basic research on baseband processor development. It is verified by comparing the bit error rate of the DSP prototype with that of a computer simulation.

• Journal of Electrical Engineering and Technology
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• v.6 no.3
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• pp.375-383
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• 2011

This paper describes a real-time hardware simulator for a grid-tied Permanent Magnet Synchronous Generator (PMSG) wind power system, which consists of an anemometer, a data logger, a motor-generator set with vector drive, and a back-to-back power converter with a digital signal processor (DSP) controller. The anemometer measures real wind speed, and the data is sent to the data logger to calculate the turbine torque. The calculated torque is sent to the vector drive for the induction motor after it is scaled down to the rated simulator power. The motor generates the mechanical power for the PMSG, and the generated electrical power is connected to the grid through a back-to-back converter. The generator-side converter in a back-to-back converter operates in current control mode to track the maximum power point at the given wind speed. The grid-side converter operates to control the direct current link voltage and to correct the power factor. The developed simulator can be used to analyze various mechanical and electrical characteristics of a grid-tied PMSG wind power system. It can also be utilized to educate students or engineers on the operation of grid-tied PMSG wind power system.

• Journal of the military operations research society of Korea
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• v.2 no.1
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• pp.185-194
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• 1976

A terminal response time analysis for a general class of terminals-to-computer subsystem is presented in this paper. On the point of the front view, it should be considered for R.O.K. Military Defense to set up the communication network in order to facilitate for the currency of the information and the data communication system. The model used to study is based on the advanced data communications system in which terminals are connected to Terminal Control Units(TCU) that are in turn connected to local Front-End Processor(FEP). The line control procedures used to interface a TCU and an FEP may be half-duplex Binary Synchronous Communication(BSC), half-duplex Synchronous Data Link Control(SDLC), or full-duplex SLDC. This paper will contribute to facilitate the initial phase of system design and configuration for the Military Defense Communication Network System in future.

• Journal of IKEEE
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• v.15 no.1
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• pp.15-22
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• 2011

In order to performing the joint operation of Korean army efficiently, informations about surveillance, reconnaissance, and situation awareness need to be possessed jointly. In the first development phase (basis type) of the Korean joint tactical data link system (JTDLS-K), essential tactical information and recognized situation are owned among platforms in common by using existing wireless terminals. In the second development phase (completion type) of the JTDLS-K, a JTDLS which can perform network centric warfare (NCW) will be developed in due consideration of technology development of the basis type and common technology maturity degree. This is a joint battlefield system that can show fighting power simultaneous and polysynthetically through providing command and control messages effectively to each platform, which is participating in the joint and combined operations. In this paper, the development of JTDLS-K with a common data processor based on common link integration processing (CLIP) is described. From the test results of the system presented in this paper, it is demonstrated that quadrature phase shift keying (QPSK) signals can be applied to the system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.55-62
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• 2005

In this paper, we propose an efficient symbol detection algorithm for space-frequency OFDM (SF-OFDM) transmit diversity scheme and present the implementation results of the SF-OFDM WLAN baseband processor with the proposed algorithm. When the number of sub-carriers in SF-OFDM scheme is small, the interference between adjacent sub-carriers may be generated. The proposed algorithm eliminates this interference in a parallel manner and obtains a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at $BER=10^{-4}$ the proposed algorithm obtains about 3 dB gain over the conventional detection algorithm. The packet error rate (PER), link throughput, and coverage performance of the SF-OFDM WLAN with the proposed detection algorithm are also estimated. For the target throughput at $80\%$ of the peak data rate, the SF-OFDM WLAN achieves the average SNR gain of about 5.95 dB and the average coverage gain of 3.98 meter. The SF-OFDM WLAN baseband processor with the proposed algorithm was designed in a hardware description language and synthesized to gate-level circuits using 0.18um 1.8V CMOS standard cell library. With the division-free architecture, the total logic gate count for the processor is 945K. The real-time operation is verified and evaluated using a FPGA test system.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1285-1288
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• 2002

Bluetooth wireless technology is a publicly available specification proposed for Radio Frequency (RF) communication for short-range and point-to- multipoint voice and data transfer. It operates in the 2.4GHz ISM(Industrial, Scientific and Medical) band and offers the potential for low-cost, broadband wireless access for various mobile and portable devices at range of about 10 meters. In this paper, we describe the structure and the test results of the bluetooth baseband module we have developed. This module was developed based on IP reuse. So Interface of each module such as link controller UART, and audio CODEC is designed based on ARM7 comfortable processor. We also considered various interfaces of related external chips. The fully synthesizable baseband module was fabricated in a $0.25{\mu}m$ CMOS technology occupying $2.79{\times}2.8mm^2$ area including the ARM TDMI processor. And a FPGA implementation of this module is tested for file and bit-stream transfers between PCs.

• The KIPS Transactions:PartA
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• v.12A no.5 s.95
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• pp.421-426
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• 2005

In a large scale parallel computation, some processor or communication link failure results in a waste of huge amount of CPU hours. However, MPI in its current specification gives the user no possibility to handle such a problem. In this paper, we propose an application-level fault tolerant linear system solver by using an MPMD-type asynchronous iteration, purely on the basis of the MPI standard without using any non-standard fault-tolerant MPI library.

• Journal of rehabilitation welfare engineering & assistive technology
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• v.11 no.1
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• pp.63-71
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• 2017

In this paper, a signal processing circuit for semi-implantable middle ear hearing device is designed using the TCBT which is recently proposed for a new middle ear transducer that can be implanted at round window of cochlea. The designed semi-implantable hearing device transmits digital sound signal from external device located at behind the ear to the internal device implanted under the skin using inductive coupling link methods with high efficiency. The coils and signal processing circuits are designed and implemented considering the total transmission and reception distance including skin thickness of temporal bone for the semi-implantable hearing device. And also, to improve the data transmission efficiency, the output circuits which can supply sufficient signal power is designed. In order to confirm operation of semi-implantable hearing device using inductive coupling link, the circuit analysis was performed using PSpice, and the performance was verified by implementing a signal processing board of an available size.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.6 no.2
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• pp.178-182
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• 2005

The proposed system in this paper is designed to provide users with a means of global location information using Orbcomm satellite communication and X.400 protocol. The system's two-way data transmission capabilities allow users to track mobile or fixed objects anywhere in the world via Internet. This study utilizes the X.400 protocol, and the SIP(Serial Interface Protocol) and self defined control protocol to implement data communication link in this paper. Data processor board connected to SC(Subscriber Communicator) is also designed and implemented to interface with GPS receiver. The experimental results of the proposed global position location system is evaluated through real-time experiments, and we have confirmed it works well according to the protocol designed in this paper.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.98-109
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• 2002

Bluetooth technology is a publicly available specification proposed for Radio Frequency (RF) communication for short-range :1nd point-to-multipoint voice and data transfer. It operates in the 2.4㎓ ISM(Industrial, Scientific and Medical) band and offers the potential for low-cost, broadband wireless access for various mobile and portable devices at range of about 10 meters. In this paper, we describe the structure and the test results of the bluetooth baseband module with direct memory access method we have developed. This module consists of three blocks; link controller, UART interface, and audio CODEC. This module has a bus interface for data communication between this module and main processor and a RF interface for the transmission of bit-stream between this module and RF module. The bus interface includes DMA interface. Compared with the link controller with FIFOs, The module with DMA has a wide difference in size of module and speed of data processing. The small size module supplies lorr cost and various applications. In addition, this supports a firmware upgrade capability through UART. An FPGA and an ASIC implementation of this module, designed as soft If, are tested for file and bit-stream transfers between PCs.