• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.412-415
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• 1999

In this paper, we describe an implementation of the B-Link bus interface logic for a directory controller and a remote access cash controller in the SCI-based CC-NUMA multimedia server developed by ETRI . The CC-NUMA multimedia server is composed of a number of Pentium III SHV nodes and a SCI interconnection network. To communicate with remote nodes, each node has a CC-Agent which consists of a processor bus interface(PIF). a directory controller(DC), a remote access cash controller(RC), and two SCI 1ink controllers(LCs). The B-Link bus interface logic is developed for a directory controller and a remote access cash controller in order to communicate with a SCI link controller on a B-Link bus. It consists of a sending master controller a receiving slave controller, and asynchronous data buffers. And It performs a self-arbitration, a data packet transmission, a queue allocation, an early terminal ion. and a cut-through data path.

• Journal of Advanced Navigation Technology
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• v.5 no.2
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• pp.149-157
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• 2001

A high speed data link capability is one of the critical factors in determining the performance of the spaceborne SAR system with high resolution. It is due to the strict requirement for the real-time data transmission from a series of massive raw image data of spaceborne SAR to the ground station in a limited time of mission. In this paper, based on the data link model characterized by the spaceborne small SAR system, the high rate multi-channel data link module is designed including link storage, link processor, transmitter, and wide-angle antenna. The design results are presented with the performance analysis on the data link budget as well as the multi-mode data rate in association with the SAR imaging mode of operation from high resolution to the wide swath.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.8
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• pp.1549-1560
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• 2009

In the TDMA PON system, the DBA is essential for ONUs to send data efficiently to the upstream. In this paper, we implement a DBA processor for the G-PON OLT with downstream and upstream rate, 2.5 and 1.25 Gbps, respectively, The processor collects bandwidth request messages from ONUs at every cycle time and allocates properly bandwidth to each Alloc-ID with considering priority and fairness for traffics. In the proposed DBA algorithm, one cycle time consists of multiple G-PON frames ($m{\times}125{\mu}s$) for high link efficiency. In particular, the link efficiency is higher because the algorithm adopts a method that an additional overhead is eliminated when an allocated bandwidth is laid between two G-PON frames for an ONU. This enables that the processor flexibly allocates the bandwidth from zero to the maximum link capacity for an ONU. The proposed DBA processor is implemented with the FPGA and shows bandwidth allocating processes for ONUs with logic analyzer.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.3
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• pp.117-124
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• 2002

A high speed data link capability is one of the critical factors in determining the performance of the spaceborne SAR system with high resolution because of the strict requirement for the real-time data transmission of the massive SAR data in a limited time of mission. In this paper, based on the data link model characterized by the spaceborne small SAR system, the high rate multi-channel data link module is designed including link storage, link processor, transmitter, and wide-angle antenna. The design results are presented with the performance analysis on the data link budget as well as the multi-mode data rate in association with the SAR imaging mode of operation from high resolution to the wide swath. The designed data link module can be effectively used for the spaceborne and airborne applications which requires to expand the high speed data link capability.

• Bulletin of the Korean Space Science Society
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• 2004.10b
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• pp.364-367
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• 2004

This paper presents the flight software of KoDSat (KSLV-l Demonstration Satellite) which performs demonstrating the KSLV-l (Korea Space Launch Vehicle-l)'s satellite launch capability. The KoDSat Flight Software executes in a single-processor, multi-function flight computer on the spacecraft, the OBC (On Board Computer). The flight software running on the single processor is responsible for all real-time processing associated with: processor startup and hardware initialization, task scheduling, RS422 handling function, command and data handling including uplink command and down-link telemetry, attitude determination and control, battery state of charge monitoring and control, thermal control processing.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.183-186
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• 2004

The proposed system in this paper utilizes the SIP and self-defined control protocol to provide global wireless communication over the data link of Orbcomm system. Main processor board connected to Orbcomm communication subscriber is designed to interface with digital I/O and AD/DA convertor for various application of control and .measurement. Hardware system implemented in this paper also includes the function of real-time clock and position report using GPS receiver The experimental result of the proposed global wireless communication system is evaluated via real-time experiments, and we have confirmed it works well according to the protocol designed in this paper.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04b
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• pp.172-174
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• 2002

XML을 기반으로 하는 가상문서는 다양한 데이터의 공유를 가능하게 하여 새로운 지식을 생성할 수 있도록 한다. 가상 문서를 지원하는 디지털 도서관 시스템에서 질의 링크는 인터넷 상의 정형데이터 공유를 가능하게 한다. 본 연구에서는 질의링크를 포함하는 XML- 기반 가상문서를 효과적으로 생성하기 위해 질의링크 생성기와 스키마 처리기를 설계하고 구현하였으며 이를 지원하기 위해 디지털 도서관 시스템과 가상문서 저작시스템에서 서비스 관리기, 메타 검색기, 데이터베이스 관리기와 저작도구를 확장하였다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.10
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• pp.1617-1623
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• 1989

The introduction of the fast Fourier transform(FFT),an efficient computational algorithm for the discrete Fourier transform(DFT) by Cooley and Tukey(1965), has brought to the limelight various other discrete transforms. Some of the analog functions from which these transforms have been derived date back to the early 1920's, for example, Walsh functions (Walsh, 1923) and Hadamard Transform(Enomoto et al, 1965). Fast algorithms developed for the forward transform are equally applicable, exept for minor changes, to the inverse transform. In this paper, we present a simple pipelined Hadamard matrix(HM) which is used to develop a fast algorithm for the Hadamard Processor (HP). The Fast Hadamard Transform(FHT) can be derived using matrix partitioning techniques. The HP system is incorporated through a modular design which permits tailoring to meet a wide range of video data link applications. Emphasis has been placed on a low cost, a low power design suitable for airbone system and video codec.