• 제목/요약/키워드: Data Link Interface

검색결과 150건 처리시간 0.01초

SCI 연결망의 B-Link 인터페이스 회로 구현 (Implementation of a B-Link Interface Logic for a SCI Interconnect)

  • 한종석;모상만;기안도;한우종
    • 대한전자공학회:학술대회논문집
    • /
    • 대한전자공학회 1999년도 추계종합학술대회 논문집
    • /
    • pp.412-415
    • /
    • 1999
  • In this paper, we describe an implementation of the B-Link bus interface logic for a directory controller and a remote access cash controller in the SCI-based CC-NUMA multimedia server developed by ETRI . The CC-NUMA multimedia server is composed of a number of Pentium III SHV nodes and a SCI interconnection network. To communicate with remote nodes, each node has a CC-Agent which consists of a processor bus interface(PIF). a directory controller(DC), a remote access cash controller(RC), and two SCI 1ink controllers(LCs). The B-Link bus interface logic is developed for a directory controller and a remote access cash controller in order to communicate with a SCI link controller on a B-Link bus. It consists of a sending master controller a receiving slave controller, and asynchronous data buffers. And It performs a self-arbitration, a data packet transmission, a queue allocation, an early terminal ion. and a cut-through data path.

  • PDF

A Development of Satellite Communication Link Analysis Tool

  • Ayana, Selewondim Eshetu;Lim, SeongMin;Cho, Dong-Hyun;Kim, Hae-Dong
    • Journal of Astronomy and Space Sciences
    • /
    • 제37권2호
    • /
    • pp.117-129
    • /
    • 2020
  • In a Satellite communication system, a link budget analysis is the detailed investigation of signal gains and losses moving through a channel from a sender to receiver. It inspects the fading of passed on data signal waves due to the process of spreading or propagation, including transmitter and receiver antenna gains, feeder cables, and related losses. The extent of the proposed tool is to make an effective, efficient, and user-friendly approach to calculate link budget analysis. It is also related to the satellite communication correlation framework by building up a graphical interface link analysis tool utilizing STK® software with the interface of C# programming. It provides better kinds of graphical display techniques, exporting and importing data files, printing link information, access data, azimuth-elevation-range (AER), and simulation is also possible at once. The components of the link budget analysis tool include transmitter gain, effective isotropic radiated power (EIRP), free space loss, propagation loss, frequency Doppler shift, flux density, link margin, elevation plot, etc. This tool can be useful for amateur users (e.g., CubeSat developers in the universities) or nanosat developers who may not know about the RF communication system of the satellite and the orbital mechanics (e.g., orbit propagators) principle used in the satellite link analysis.

Link-22 SNC 연동을 위한 전술데이터링크 처리 구조 확장 개선 연구 (A Study on the Expansion and Improvement of the Tactical Data Link Processing Structure for Link-22 SNC Interface)

  • 정석호;황정은;이윤정;박지현
    • 한국전자통신학회논문지
    • /
    • 제16권6호
    • /
    • pp.1045-1052
    • /
    • 2021
  • 현대전은 감시체계, 지휘통제체계, 타격체계가 첨단 정보통신기술로 상호 연결되어 전장상황을 공유하는 네트워크 중심전(NCW: Network Centric Warfare)으로 변화해 가고 있다. 한국군은 각 군의 전장상황에 맞게 Link-K, Link-16, Link-11, KVMF 등 다양한 전술데이터링크(TDL: Tactical Data Link)를 활용하고 있다. 한국형 합동 전술데이터링크체계(JTDLS : Joint Tactical Data Link System)는 지상/해상/공중 합동전력간 근실 시간으로 전술정보를 공유하는 체계로 Link-K, Link-16, KVMF에 Link-22를 추가 개발하고 있다. 본 논문에서는 JTDLS체계에 Link-22를 적용하기 위하여 체계 구성, Link-22 메시지 분석 및 전술 데이터 링크 처리기와 Link-22의 연동 구조를 제시하고자 한다.

A Link Layer Design for DisplayPort Interface

  • Jin, Hyun-Bae;Yoon, Kwang-Hee;Kim, Tae-Ho;Jang, Ji-Hoon;Song, Byung-Cheol;Kang, Jin-Ku
    • 전기전자학회논문지
    • /
    • 제14권4호
    • /
    • pp.297-304
    • /
    • 2010
  • This paper presents a link layer design of DisplayPort interface with a state machine based on packet processing. The DisplayPort link layer provides isochronous video/audio transport service, link service, and device service. The merged video, audio main link, and AUX channel controller are implemented with 7,648 LUTs(Loop Up Tables), 6020 register, and 821,760 of block memory bits synthesized using a FPGA board and it operates at 203.32MHz.

전자연동장치와 역정보전송장치간 인터페이스를 위한 데이터링크 프로토콜 성능해석 (Performance Analysis of Data Link Protocol for Interface between EIS and LDTS)

  • Hwang, Jong-Gyu;Lee, Jae-Ho
    • 한국철도학회논문집
    • /
    • 제6권2호
    • /
    • pp.135-141
    • /
    • 2003
  • According to the computerization of railway signaling systems, the interface link between these signaling equipment is also replaced by digital communication channel, expecially communication link for interface between EIS and LDTS, but there are some problems in the present state of railway signaling. First of all, different communication protocol is applied to interface between above two signaling equipment although they have same functions. The other is that the communication protocol currently used in railway field has some unreasonable points such as structure, formation of byte, error correction scheme and etc. To solve these problems, the standard communication protocol for railway signaling is designed. The structure of designed communication protocol and the results of performance analyses are represented in this paper. It will be expected the increase of safety, reliability and efficiency of maintenance of signaling system by using of the designed communication protocol for railway signaling.

MPEG2용 IEEE1394 LINK CHIP SET 개발 기술

  • 이희
    • 정보화사회
    • /
    • 통권129호
    • /
    • pp.42-49
    • /
    • 1999
  • 디지털 비디오의 혁명이 가시화 되면서 가정의 각 Consumer기기들 간의 고속 Digital Interface가 요구되어져 왔다. 이러한 요구의 예는 MPEG-2 Transport Stream을 이용한 Set-Top Bx, Digital Television, DVCR 또는 Camcorder간의 Interface와 Interactive Games, Computers 및 주변기기간의 Control/Data Interface를 포함하고 있다. 엄밀히 말해 Data의 일반적인 전송을 지원하는 Interface가 요구되어지며, IEEE1394 Standard는 이에 대한 최적의 Solution을 제공해 준다. 본 기술은 IEEE1394를 기반으로 MPEG-2 Transport Stream을 주고받을 수 있는 방법을 제공하기 위한 Hardware를 개발하는 기술인 MPEG2용 IEEE1394 Link Chip Set 개발 기술에 대하여 설명한다.

  • PDF

함정 전투체계 전술데이터링크 개발현황 및 메시지 분석 (Message Analysis and Development Situation on the Tactical Data Link of Combat Management System in Naval)

  • 유호정;최병곤
    • 한국위성정보통신학회논문지
    • /
    • 제12권2호
    • /
    • pp.21-27
    • /
    • 2017
  • 국내 개발 함정 전투체계는 Link-11, 위성ISDL, JTDLS(합동전술데이터링크) 등 다종의 전술데이터링크를 운용하고 있으며, 각 전술데이터링크는 고유의 메시지를 이용하여 전술데이터링크로 표적, 교전 및 무장정보 등과 같은 전술정보를 전달할 수 있다. 함정에서 운용되는 다종의 전술데이터링크는 복수의 전술상황도(CTP), 주요기능 중복으로 업무효율성을 저하시키는 단점이 상존해 있으며, 선진국에서는 이를 극복하기 위해 전술데이터링크를 통합형 구조로 변경하는 추세에 있다. 현재 함정 전투체계에서는 위성ISDL, KNCCS, JTDLS 체계가 해군전술C4I 성능개량체계로 통합되어 운용될 예정이다. 본 논문에서는 국내 개발 함정 전투체계 전술데이터링크 개발현황을 고찰하고, 해군전술C4I 성능개량체계의 Host Interface 메시지와 위성ISDL의 I 메시지를 비교분석하여 해군전술C4I 성능개량체계의 발전사항에 대하여 제시하고자 한다.

Fieldbus 네트워크 접속기의 하위계층 구현 (Lower layer implementation of a fieldbus network interface)

  • 김현기;이전우;황선호;이혁희;채영도
    • 제어로봇시스템학회:학술대회논문집
    • /
    • 제어로봇시스템학회 1991년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 22-24 Oct. 1991
    • /
    • pp.337-341
    • /
    • 1991
  • Fieldbus is a low level serial digital network which will be used for factory automation. This paper describes lower layer implementation of a Fieldbus network interface. Physical layer provides hardware interface between IBM-PC and Fieldbus. Also, physical layer uses manchester coding, shielded twisted pair lines and RS-485 electrical standard. Data link layer includes Intel's iDCX96 real time executive for 8797 one chip microcontroller and Fieldbus data link protocol software.

  • PDF

FOUNDATION 필드버스 인터페이스 보드 구현 (Implementation of FOUNDATION Fieldbus Interface Board)

  • 최인호;홍승호
    • 제어로봇시스템학회:학술대회논문집
    • /
    • 제어로봇시스템학회 2000년도 제15차 학술회의논문집
    • /
    • pp.93-93
    • /
    • 2000
  • In this study, physical and data link layer protocols of FOUNDATION Fieldbus are implemented. INTEL386EX and 80196KC are used fer the CPU of PC interface board and sensor interface module, respectively The physical layer protocol of FOUNDATION Fieldbus is developed by using FB3050 chip, the fieldbus communication controller ASIC. The data Link layer protocol of FOUNDATION Fieldbus is implemented by software.

  • PDF

Design and Analysis of Ethernet Aggregation to XGMII Framing Procedure

  • Kim, You-Jin;Huh, Jae-Doo
    • 한국정보기술응용학회:학술대회논문집
    • /
    • 한국정보기술응용학회 2005년도 6th 2005 International Conference on Computers, Communications and System
    • /
    • pp.331-334
    • /
    • 2005
  • This paper suggests the Ethernet aggregation to XGMII framing procedure (EAXFP) mechanism to economically combine the traffic adaptation technology with the link aggregation method in designing 10 Gigabit Ethernet (10 GbE) interfaces. This design sidesteps the data-loss issues that can result from designing an interface with only one link. The most critical issue in relation to the link aggregation interface is the algorithm used to control frame distribution between the ten ports. The proposed EAXFP mechanism offers an efficient link aggregation method as well as an efficient frame distribution algorithm, which maximize the throughout of the 10 GbE interface. In the experiment and analysis of the proposed mechanism, it was also discovered that the 10 GbE interface that uses the proposed EAXFP mechanism significantly reduced the packet loss rate. When there will be heavy traffic loads come about in the future, the proposed EAXFP mechanism assures an efficient and economical transmission performance on the router system.

  • PDF