• Journal of the Institute of Convergence Signal Processing
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• v.5 no.4
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• pp.325-332
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• 2004

In this paper, we propose a new DSSS-QPSK baseband modem receiver structure. A general receiver consists of matched filter, do-spreader, and DLL(Delay Locked Loop). In this paper, the matched filter plays a role of the do-spreader using the structure similarities between the matched filter and the de-spreader. As a result of the new receiver architecture, we can reduce the computational expenses and get the simpler receiver structure. This result can be used as an important part in designing the high speed modem. And, through the computer simulation and the experiment with the proposed architecture, we show that the proposed receiver structure yields fast operation speed and simple overall architecture.

• Journal of IKEEE
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• v.12 no.2
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• pp.95-101
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• 2008

In this paper, we study an optimum design of search synchronization structure for Baseband Modem to support ISO/IEC 18185-5 and 24730-2 Standard. For DSSS Modem, we design the code acquisition and tracking structure which are important in receiver operation, and examine the parameters to be considered. The data and PN chip transmission rates and processing gain of the proposed modem are 59.7 kbps, 30.521875 Mcps, and 27 dB, respectively. This indicates that the noise immunity of the proposed modem is 17dB better than IEEE 802.11b (Processing gain : 10dB). Therefore, we design the optimum structure for the modem search synchronization which is compatible to the proposed modem standard.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.121-126
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• 2006

This paper report on the design and implementation of a 9.6kbps DSSS CDMA modem for a medium speed wireless link. The proposed modem provides a general purpose I/O interface with a microprocessor. The I/O interface consists of 8-bit data bus, chip enable, read/write, and interrupt pins. In transmit block, the 8-bit data delivered from the I/O interface buffer is converted to 9.6kbps serial data, which are spreaded into 76.8kcps with 8-bit PN code generated inside the modem by direct sequence method. An 8-bit training sequence is preceded in the data frame for data synchronization in receiver. In receiver block the PN code is synchronized from the received data spreaded to 76.8kcps and find the data timing from the 8-bit training sequence. We have used the Early-and-Late integration method. The modem has been implemented and verified using a Xilix FPGA board and has been fabricated as an ASIC CHIP through Hynir $0.25{\mu}m$ CMOS. The multiple accessing method is DSSS CDMA.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.2
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• pp.116-123
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• 2005

Chirp spread spectrum method using both time and frequency component is fit to time varying channel such as powerline channel. The used chirp symbol based on the CEBus standard is the unit symbol which sweeps from 100kHz to 380kHz over a 25㎲. To evaluate the performance of between Chirp-SS and DSSS, we measured the bit error rate under Gaussian channel. Simulation result is shown that Chirp-SS has a about 3[dB] gain of SNR than DSSS. To verify the performance of implemented modem, it is made up the powerline channel environment. After adding several noises to it, we examined the receiving status of modem. The implemented modem is able to receive the signal over the powerline channel with having several noises and capacitive loads.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.18-26
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• 1999

This paper presents the architecture and design of a DSSS MODEM ASIC chip for wireless local area networks (WLAN). The implemented MODEM chip supports the DSSS physical layer specifications of the IEEE 802.11. The chip consits of a transmitter and a receiver which contain a CRC encoder/decoder, a differential encoder/decoder, a frequency offset compensator and a timing recovery circuit. The chip supports various data rates, i.e., 4,2 and 1Mbps and provides both DBPSK and DQPSK for data modulation. We have performed logic synthesis using the $SAMSUNG^{TM}$ $0.6{\mu}m$ gate array library and the implemented chip consists of 53,355 gates. The MODEM chip operates at 44MHz, the package type is 100-pin QFP and the power consumption is 1.2watt at 44MHz. The implemented MODEM architecture shows lower BER compared with the Harris HSP3824.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.582-590
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• 1994

This paper introduce a highly verstile and simple data transmission system designed for commercial power distribution lines. The system operates on the DSSS principle but utilizes two independent carrier frequencies each represents polarity of DS MODEM outiputs. At the receiving terminal, outputs of two envelope detectors are directly applied to separate DS correlators before the two components are compared. The recovered signals which represents data and line noise are then compared at comparator. With the noise power greatly rudused at the correlator, the error rate of the data observed at comparator desplays great improvement comparing to the conventional FSK-DS system in which the detector output are compared before the correlator stage. Despite its simplest structure, the prototype MODEM transmitts 2400 bps with the error rate 10 , about 10dB improved compared to conventional FSK system.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.8
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• pp.1-9
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• 2009

In this paper, we describe DSSS transceiver development robust to jamming signals as an investigation of ECCM transceiver for UAV uplink. The jamming margin is 15dB or greater with the development target of transceiver because the jamming margin is more important than the transmission rate of data and the spreading code can be changeable. The rake receiver is applied to combine multipath components and turbo code which the coding gain is 7.2dB as a FEC. In this paper, the whole structure, design method and functional test result about the designed modem are described and a conclusion is made.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2637-2639
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• 2002

This paper presents the design and implementation of a baseband Modem using DSP that supports a wireless LAN. It is implemented with DSP and D/A and A/D Converters in baseband and tested without using IF and RF modules. In this paper, we have used the matched filler and DLL(delay lock loop) for synchronization. And the matched filter and the carrier recovery are directly connected. Therefore, the proposed architecture is very simple and the operation of DSP becomes fast.

• ETRI Journal
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• v.33 no.4
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• pp.528-536
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• 2011

In this paper, we analyze the location accuracy of real-time locating systems (RTLSs) in multipath environments in which the RTLSs comply with the ISO/IEC 24730-2 international standard. To analyze the location error of RTLS in multipath environments, we consider a direct path and indirect path, in which time and phase are delayed, and also white Gaussian noise is added. The location error depends strongly on both the noise level and phase difference under a low signal-to-noise ratio (SNR) regime, but only on the noise level under a high SNR regime. The phase difference effect can be minimized by matching it to the time delay difference at a ratio of 180 degrees per 1 chip time delay (Tc). At a relatively high SNR of 10 dB, a location error of less than 3 m is expected at any phase and time delay value of an indirect signal. At a low SNR regime, the location error range increases to 8.1 m at a 0.5 Tc, and to 7.3 m at a 1.5 Tc. However, if the correlation energy is accumulated for an 8-bit period, the location error can be reduced to 3.9 m and 2.5 m, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2C
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• pp.175-183
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• 2006

This letter proposes a Direct Sequence Spread Spectrum (DS-SS)-based Flight Termination System(FTS) and show the simulation results and implements the system using FRGAs. The DS-SS FTS has immunity interference signals and the influence of jamming signal. Moreover, a DS-SS FTS can provides effects on an authentication and encryption with spread codes. And the system uses more less power than an analog FM system. We used Reed-Solomon (32, 28) code and triple Data Encryption Standard(3DES) for error correction and data encryption. Also we used counter algorithm for unauthenticated device's attack The spread codes of In-phase channel and Quadrature channel were generated by Gold sequence generators. The system was implemented in Altera APEX20K100E FPGA for the ground system and EPF10K100ARC240-3 for the airborne system.