• Title/Summary/Keyword: DSP(digital signal processor)

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Implementation of Random Carrier-Frequency Modulation Scheme for a DSP based PWM Inverter for Acoustic Noise Reduction of Induction Motors (유도전동기의 소음저감을 위한 DSP기반 PWM인버터의 랜덤 캐리어 주파수 변조기법의 구현)

  • 정영국;나석환;임영철;정성기
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.52 no.12
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    • pp.608-615
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    • 2003
  • This paper describes an implementation of a DSP (Digital Signal Processor) controlled random carrier frequency modulation for the PWM inverter for acoustic noise reduction of induction motors. Real-time generation of the random variable and RPWM(Random PWM) along with the speed control was achieved by DSP TMS320C31. The experimental results show that the voltage and current harmonics are spread to a wide band area and the power spectrum of the acoustic switching noise was spread to create a more appealing, less annoying sound. Also, the speed response of the implemented method and the conventional method is nearly similar to each other from the viewpoint of the v/f constant control.

Development of a DSP Control Board for Electroplating Power System (전기도금용 전원장치구동을 위한 DSP 탑재 제어보드의 개발)

  • Song, Ho-Shin;Lee, Dae-Hee;Bae, Jong-Moon;Lee, Oh-Guel;Noh, Sung-Chae
    • Proceedings of the KIEE Conference
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    • 2000.07d
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    • pp.2551-2553
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    • 2000
  • 고속 신호처리 및 실시간 제어 분야에 적합한 제어성능을 발휘하기 위해서는 신호처리전용 마이크로프로세서인 DSP(Digital Signal Processor)를 이용한 제어용 보드가 널리 활용되고 있다. 본 연구를 통하여 전기도금용 전원장치의 고성능화를 위하여 DSP제어용 보드를 개발하였으며, 전체구성은 고속 신호처리를 위한 메인 마이크로프로세서로서 경제성과 응용범위가 넓은 TMS320C32 DSP CHIP, Wait없는 프로그램 및 데이터 처리를 위한 고속 SRAM, 외부 디지털 입출력을 위한 인터페이스 회로, 아나로그 입출력 회로 및 PC 혹은 다른 마이크로컴퓨터와의 통신을 위한 직렬 통신 회로 등으로 구성하였다. 개발된 DSP 보드는 시제품 제작을 완료하여 그 성능 및 신뢰성을 검증하였으며, 전기도금장치의 고성능 제어처리를 위하여 채용하여 상품화 개발을 완료하였다.

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Implementation of the Wireless Sanjo Gayageum Based on Physical Modeling Using Arduino and DSP (아두이노와 DSP를 이용한 물리적 모델링 기반의 현 없는 산조 가야금 구현)

  • Seo, Jun-Sang;Jung, In-Kyu;Kim, Jong-Myon
    • Proceedings of the Korean Society of Computer Information Conference
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    • 2014.01a
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    • pp.19-21
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    • 2014
  • 본 논문에서는 기존의 산조가야금의 음을 합성하여 아두이노(Arduino)와 DSP(Digital Signal Processor)를 이용한 물리적 모델링 기반의 현 없는 산조 가야금을 구현한다. 아두이노는 저렴한 가격에 마이크로컨트롤러를 효율적으로 제어하며, DSP는 높은 분해능과 빠른 A/D변환 기능을 지원하여 복잡한 음 합성 연산의 빠른 처리를 만족시킨다. 또한 기존 가야금의 복잡한 연주법을 초보자도 쉽게 다루기 위해 가야금의 현을 대신해 터치 패널을 사용한다. 본 논문에서는 기본적인 I/O동작은 아두이노 MEGA 2560보드를, 음 합성의 복잡한 연산을 위해 CCSv5(Code Composer Studio) 툴과 DSP칩을 내장한 DSK5510 보드를 이용하여 기능을 검증한다. 모의실험 결과 현 없는 가야금의 합성음은 기존의 음과 매우 유사하였으며, 초보자도 쉽게 제어하고 연주가 가능한 환경을 구현하였다.

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A Study on the Design of the Digital Filter Bank Using the Wave Digital Filters (웨이브 디지탈 필터를 이용한 디지탈 필터뱅크의 설계에 관한 연구)

  • 임덕규;한인철;이재석;이종각
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.13 no.2
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    • pp.107-119
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    • 1988
  • An 8-channel digital filter bank with wave digital filters(WDF) is studied. Wave digital filtwr is automatically a directional filter. Using these properties, a new method for organizing the 8-channel digital filter bank is proposed. This will lead to enormous savings in memories for the digital signal processign chip.

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Sliding mode control of manipulator whose nonlinear components are regarded as external disturbance (비선형 성분을 외한으로 간주했을때의 매니퓰레이터의 슬라이딩 모드제어)

  • ;Aoshima, Nobuharu
    • 제어로봇시스템학회:학술대회논문집
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    • 1991.10a
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    • pp.286-291
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    • 1991
  • This paper discusses sliding made control of robot manipurators assuming that nonlinear terms, which are inertia term, Coriolis force term and centrifugal taffn, are external disturbances. We obtained the unknown parameter of its linear terms by Signal Compression Method. We propose a new control input algorithm to decrease chattering in the application of sliding mode control of manipulator whose nonlinear components are regarded as disturbances. In this experiments, we used DSP(Digital Signal Processor) controller to suppress chattering by obtaining a quick switching speed.

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MOBILE WIMAX 기반 향상된 다중 안테나 시스템의 고정소수점 설계

  • Kim, Hak-Min;Ahn, Chi-Young;Yun, Yu-Suk;Jung, Jae-Ho;Choi, Seung-Won
    • 한국정보통신설비학회:학술대회논문집
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    • 2008.08a
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    • pp.409-413
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    • 2008
  • In this paper, we introduce a platform of advanced multiple antenna system based on orthogonal frequency-division multiplexing (OFDM). The advanced multiple antennas have beamforming gain using array antenna. In array antenna systems, received signal has phase delay caused distance of each antennas, therefore it should compensate with optimum weight vector which calculated by Lagrange algorithm. To implement the presented above procedures using Digital Signal Processor (DSP), we should fixed-point design. The performance of implemented platform is verified through MATLAB$^{(R)}$ simulations with various signal environments.

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Implementation of Spectrum Analysis System for Vibration Monitoring

  • Nguyen, Thanh Ngoc;Jeon, Taehyun
    • International Journal of Internet, Broadcasting and Communication
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    • v.11 no.2
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    • pp.27-30
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    • 2019
  • Factory monitoring systems are gaining importance in wide areas of industry. Especially, there have been many efforts in implementation of vibration measurement and analysis for monitoring the status of rotating machines. In this paper, a digital signal processor (DSP) based monitoring system dedicated to the vibration monitoring and analysis on rotating machines is discussed. Vibration signals are acquired and processed for the continuous monitoring of the machine status. Time domain signals and fast Fourier transform (FFT) are used for vibration analysis. All of the signal processing procedures are done in the DSP to reduce the production and maintenance cost. The developed system could also provide remote and mobile monitoring capabilities to operator via internet connection. This paper describes the overview of the functional blocks of the implemented system. Test results based on signals from small-size single phase motors are discussed for monitoring and defect diagnosis of the machine status.

Real-Time Implementation of a SBC Codec Using a NEC 7720 DSP (NEC 7720 DSP를 이용한 SBC codec의 실시간 구현)

  • Oh, Soo Hwan;Lee, Sang Uk
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.4
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    • pp.429-438
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    • 1986
  • In this paper we have designed and implemented a real-time, full-duplex SBC (sub-band coding) codec at 16kbps using a high speed digital signal processor, NEC 7720. The SBC codec employs a QMF(quadrature mirror filter) filter bank based on the tree structures of two-band analysis-synthesis pairs to partition speech signal into 4 octabe bands. Computer simulation has been done to investigate the effect of fixed-point computation of the NEC 7720. Three different performance measures, the conventional signal-to-noise ratio, the informal listening test, and an LPC(linear predictive coding)distance measure, have been used in this simulation. The necessary parameters have been optimized through the simulation. The developed hardware and software have been tested in real-time operation using a hardware emulator.

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A Study on Water Depth Measurement Rate Improvement using Echosounder (음향 측심기 수심인식률 향상 기법 연구)

  • Park, Dong-Jin;Kim, Young-Il;Oh, Young-Seock;Park, Seung-Soo
    • Journal of Korean Society for Geospatial Information Science
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    • v.16 no.3
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    • pp.71-78
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    • 2008
  • Nowadays, echosouder has been widely used in sea survey and ship navigation. By utilizing echosounder, we can measure the depth of water reliability. However, the problem is that depth update rate drops remarkably when sea bottom is shallow or steep/rugged. Therefore, we have developed an optimized algorithm to process tranducer's soundwave signals at high-speed and minimize error. Processing algorithm is implemented by the latest DSP processor (TMS320F2812), consequently, high-speed data processing can be achieved. Performance of the proposed algorithm is verified by experiments and compared with existing algorithms. It has shown that our method results in higher precision in water depth measurement than other methods.

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Implementation of the MPEG-1 Layer II Decoder Using the TMS320C64x DSP Processor (TMS320C64x 기반 MPEG-1 LayerII Decoder의 DSP 구현)

  • Cho, Choong-Sang;Lee, Young-Han;Oh, Yoo-Rhee;Kim, Hong-Kook
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.257-258
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    • 2006
  • In this paper, we address several issues in the real time implementation of MPEG-1 Layer II decoder on a fixed-point digital signal processor (DSP), especially TMS320C6416. There is a trade-off between processing speed and the size of program/data memory for the optimal implementation. In a view of the speed optimization, we first convert the floating point operations into fixed point ones with little degradation in audio quality, and then the look-up tables used for the inverse quantization of the audio codec are forced to be located into the internal memory of the DSP. And then, window functions and filter coefficients in the decoder are precalculated and stored as constant, which makes the decoder faster even larger memory size is required. It is shown from the real-time experiments that the fixed-point implementation enables us to make the decoder with a sampling rate of 48 kHz operate with 3 times faster than real-time on TMS320C6416 at a clock rate of 600 MHz.

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