• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.24-30
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• 2009

In this paper, the FPGA modem platform complying with 3GPP Release 7 eHSPA specifications and its regularized verification flow are proposed. The FFGA platform consists of modem board supporting physical layer requirements, MCU and DSP core embedded control board to drive the modem board, and peripheral boards for RF interfacing and various equipment interfaces. On the other hand, the proposed verification flow has been regularized into three categories according to the correlation degrees of hardware-software inter-operation, such as simple function test, scenario test call processing and system-level performance test. When it comes to real implementations, the emulation verification strategy for low power mobile SoC is also introduced.

• Journal of Broadcast Engineering
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• v.2 no.1
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• pp.8-15
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• 1997

In this paper, a real-time operating Motion Picture Experts Group-1 (MPEG-1) audio encoder system is implemented using a TMS320C31 Digital Signal Processor (DSP) chip. The basic operation of the MPEG-1 audio encoder algorithm based on audio layer-2 and psychoacoustic model-1 is first verified by C-language. It is then realized using the Texas Instruments (Tl) assembly in order to reduce the overall execution time. Finally, the actual BSP circuit board for the encoder system is designed and implemented. In the system, the side-modules such as the analog-to-digital converter (ADC) control, the input/output (I/O) control, the bit-stream transmission from the DSP board to the PC and so on, are utilized with a field programmable gate array (FPGA) using very high speed hardware description language (VHDL) codes. The complete encoder system is able to process the stereo audio signal in real-time at the sampling frequency 48 kHz, and produces the encoded bit-stream with the bit-rate 192 kbps. The real-time operation capability of the encoder system and the good quality of the decoded sound are also confirmed using various types of actual stereo audio signals.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.2
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• pp.127-134
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• 2006

This paper describes a fully hardware realization of vector controller for the permanent magnet synchronous motor (PMSM) using high density field programmable gate mays (FPGA). In the proposed system, the vector controller including vector transformation , PI regulator, position and speed measurement, current measurement, and space vector PWM blocks is implemented in a FPGA using a VHSIC hardware description language (VHDL). The experimental results using a 1.1kW PMSM are provided to show the validity of the proposed system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.12
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• pp.1252-1263
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• 2009

In this paper, in order to improve a service quality and to broaden the service coverage in the mobile communication system a study on a digital RF repeater employed with an Interference Cancellation System(ICS) is performed. The digital RF repeater employed with an ICS is implemented to remove interference and feedback signals which are disadvantages of a conventional(or general) RF repeater. This thesis presents the design and experiments of the new wireless repeater. The proposed wireless repeater consists of a RF repeater mounted with digital engine. The digital ICS engine consists of a DSP and FPGA. The digital engine and RF circuit are designed into a one-piece. After developing hardware through the digital platform they are also designed and fabricated into a one-piece in order to apply a best performance repeater system. The method of removing interference and feedback signals is an adaptive IF technique employed with a LMS algorithm. The powerful performance and fast convergence speed is obtained by using this method.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1573-1576
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• 2004

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.11
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• pp.1137-1143
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• 2009

This paper presents the FPGA implementation of efficient algorithms for approximating exponential function based on floating point format data. The Taylor-Maclaurin expansion as a conventional approximation method becomes inefficient since high order expansion is required for the large number to satisfy the approximation error. A format converter is designed to convert fixed data format to floating data format, and then the real number is separated into two fields, an integer field and an exponent field to separately perform mathematic operations. A new assembly command is designed and added to previously developed command set to refer the math table. To test the proposed algorithm, assembly program has been developed. The program is downloaded into the Altera DSP KIT W/STRATIX II EP2S180N Board. Performances of the proposed method are compared with those of the Taylor-Maclaurin expansion.

• Smart Structures and Systems
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• v.3 no.1
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• pp.69-88
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• 2007

In this study, Field-Programmable Gate Arrays (FPGAs) are investigated as a practical solution to the challenge of designing an optimal platform for implementing algorithms in a wireless sensing unit for structuralhealth monitoring. Inherent advantages, such as tremendous processing power, coupled with reconfigurable and flexible architecture render FPGAs a prime candidate for the processing core in an optimal wireless sensor unit, especially when handling Digital Signal Processing (DSP) and system identification algorithms. This paper presents an effort to create a proof-of-concept unit, wherein an off-the-shelf FPGA development board, available at a price comparable to a microprocessor development board, was adopted. Data processing functions, including windowing, Fast Fourier Transform (FFT), and peak detection, were implemented in the FPGA using a Matlab Simulink-based high-level abstraction tool rather than hardware descriptive language. Simulations and laboratory tests were carried out to validate the design.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.61 no.1
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• pp.47-54
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• 2012

This paper presents implementation of SVPWM technique for three phase Voltage Source Inverter using FPGA. Software-based vector-control calculations much this drawback, in order to improve the hardware-vector-control tries. Without the need for additional software, vector control algorithm is designed to be modular SOPC, and DSP will reduce most of the operations. In this paper, the SVPWM that using HDL for the AC motor vector control algorithm level, and the dead time part and the speed control in order to controled a speed detector and designed in the form of modules. Then ALTERA corporation Cyclone III series EP3C16F484 can be verified by implemented.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.322-325
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• 2011

스테레오 비전 시스템에서 전통적인 매칭 알고리즘으로 SAD(Sum of Absolute Differences), SSD(Sum of Squared Differences), NCC(Normalized Cross Correlation) 등 다양한 알고리즘이 존재한다. 그러나 하드웨어로 실시간 처리를 위한 시스템을 구현하기 위해서는 리소스가 한정 되어있다는 제약 때문에 많은 연구에서 SAD 혹은 RT(Rank Transform), CT(Census Transform)를 많이 사용하게 된다. FPGA 내부에는 BRAM(Block RAM)과 MAC(multiply-accumulator)인 DSP슬라이스가 이미 존재한다. 본 논문에서는 BRAM과 DSP로직을 활용해서 전통적인 매칭 알고리즘 중에서 연산기 사용이 가장 많은 NCC를 FPGA로 실시간 처리 가능한 하드웨어 구조를 제안한다.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2006.06a
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• pp.309-310
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• 2006

FPGA와 DSP기술을 이용한 여러 변복조방식을 통합하는 다기능 System-On-Chip 보드 개발하여 기존의 아날로그 방식에 비해 확장의 용이성 및 시간 인력의 절감을 가져오며, 향후 디지털 통신 실험 장치에 대한 기술력 확보등을 목표로 하고 있다.