• Title/Summary/Keyword: DRAM1

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Unusual ALD Behaviors in Functional Oxide Films for Semiconductor Memories

  • Hwang, Cheol Seong
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.77.1-77.1
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    • 2013
  • Atomic layer deposition (ALD) is known for its self-limiting reaction, which offers atomic-level controllability of the growth of thin films for a wide range of applications. The self-limiting mechanism leads to very useful properties, such as excellent uniformity over a large area and superior conformality on complex structures. These unique features of ALD provide promising opportunities for future electronics. Although the ALD of Al2O3 film (using trimethyl-aluminum and water as a metal precursor and oxygen source, respectively) can be regarded as a representative example of an ideal ALD based on the completely self-limiting reaction, there are many cases deviating from the ideal ALD reaction in recently developed ALD processes. The nonconventional aspects of the ALD reactions may strongly influence the various properties of the functional materials grown by ALD, and the lack of comprehension of these aspects has made ALD difficult to control. In this respect, several dominant factors that complicate ALD reactions, including the types of metal precursors, non-metal precursors (oxygen sources or reducing agents), and substrates, will be discussed in this presentation. Several functional materials for future electronics, such as higher-k dielectrics (TiO2, SrTiO3) for DRAM application, and resistive switching materials (NiO) for RRAM application, will be addressed in this talk. Unwanted supply of oxygen atoms from the substrate or other component oxide to the incoming precursors during the precursor pulse step, and outward diffusion of substrate atoms to the growing film surface even during the steady-state growth influenced the growth, crystal structure, and properties of the various films.

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System on Chip Policy of Major Nations (주요국의 시스템반도체 정책 및 시사점)

  • Chun, Hwang-Soo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.05a
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    • pp.747-749
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    • 2012
  • This paper is analyzing the SoC policy of major nations as the U.S, Japan, Europe, Taiwan, China and draw the suggestions for the development of semiconductor industry in Korea. SoC is the non-memory semiconductor to support and put into action the function of system. SoC is big market over the 200billion dollars and have a huge potential for new IT convergence market. Developed countries as the US, Japan, and Europe have enforced the industrial competitiveness by company investment and Taiwan supported the SoC Industry by government fund. Korea is No.1 superpower in DRAM semiconductor, but very weak in SoC Industry. We should secure the competitiveness of SoC Industry by the development of core technology, planning the growth policy, and building the cooperative model to leap the SoC power nation.

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A Study on the Properties of WS $i_{x}$ Thin Film with Formation Conditions of Polycide (폴리사이드 형성 조건에 따른 WS $i_{x}$ 박막 특성에 관한 연구)

  • 정양희;강성준;김경원
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.52 no.9
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    • pp.371-377
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    • 2003
  • We perform the physical analysis such that Si/W composition ratios and phosphorus distribution change in the W/S $i_{x}$ thin films according to phosphorus concentration of polysilicon and W $F_{6}$ flow rate for the formation of WS $i_{x}$ polycide used as a gate electrode. We report that these physical characteristics have effects on the contact resistance between word line and bit line in DRAM devices. RBS measurements show that for the samples having phosphorus concentrations of 4.75 and 6.0${\times}$10$^{2-}$ atoms/㎤ in polysilicon, by applying W $F_{6}$ flow rates decreases from 4.5 to 3.5 sccm, Si/W composition ratio has increases to 2.05∼2.24 and 2.01∼2.19, respectively. SIMS analysis give that phosphorus concentration of polysilicon for both samples have decreases after annealing, but phosphorus concentration of WS $i_{x}$ thin film has increases by applying W $F_{6}$ flow rates decreases from 4.5 to 3.5 sccm. The contact resistance between word line and bit line in the sample with phosphorus concentration of 6.0 ${\times}$ 10$^{20}$ atoms/㎤ in polysilicon is lower than the sample with 4.75 ${\times}$ 10$^{20}$ atoms/㎤ After applying W $F_{6}$ flow rates decreases from 4.5 to 3.5 sccm, the contact resistance has been improved dramatically from 10.1 to 2.3 $\mu$ $\Omega$-$\textrm{cm}^2$.

Study on resistive switching characteristics of AlN films (AlN 박막의 저항 변화 특성에 관한 연구)

  • Kim, Hee-Dong;An, Ho-Myoung;Seo, Yu-Jeong;Kim, Tae-Geun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.257-257
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    • 2010
  • 최근 저항 변화 메모리는 종래의 비휘발성 기억소자인 Flash memory보다 access time(writing)이 105배 이상 빠르고, DRAM과 같이 2~5 V 이하의 낮은 전압 특성 및 간단한 제조 공정 등으로 차세대 비휘발성 메모리 소자로 주목 받고 있지만, 여전히 소자의 Endurance 및 Retention 특성 등의 신뢰성 문제를 해결해야 할 과제로 안고 있다. 이러한 문제점들을 해결하기 위해 페로브스카이트계 산화물 또는 이원 산화물 등의 다양한 저항 변화 물질에 대한 연구가 진행되고 있다. 하지만, 현재 주로 연구되고 있는 금속 산화물계 물질들은 그 제조 공정상 산소에 의한 다수의 산소 디펙트 형성과 제작 시 쉽게 발생할 수 있는 표면 오염의 문제점을 안고 있다. 본 연구는 기존의 금속 산화물계 박막의 제조 공정에서 발생하는 문제점을 해결하기 위해 질화물계 박막을 저항변화 물질로 도입함으로써, 기존의 저항 변화 물질의 장점인 간단한 공정 및 저전압/고속 동작 특성을 동일하게 유지 할 뿐 아니라, 그 제조 공정상 발생하는 다수의 산소 디펙트와 표면 오염의 문제를 해결함으로써, 보다 고효율을 가지며 재현성이 우수한 메모리 소자를 구현 하고자 한다 [1, 2]. 본 연구를 위해 Pt/AlN/Pt 구조의 Metal/Insulator/Metal(MIM) 저항 변화 메모리를 제작 하였다. 최적의 저항 변화 특성 조건을 확인하기 위해 70~200nm까지 두께 구분과 N2 가스 분위기의 열처리 온도를 $200{\sim}600^{\circ}C$까지 진행 하였다. 본 소자의 저항 변화 특성 실험은 Keithley 4200-SCS을 이용하여 진행 하였다. 실험 결과, AlN의 최적의 두께 및 열처리 온도 조건은 130nm/$500^{\circ}C$였으며, 안정적인 unipolar 저항 변화 특성을 확인 활 수 있었다.

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Real-Time Spacer Etch-End Point Detection (SE-EPD) for Self-aligned Double Patterning (SADP) Process

  • Han, Ah-Reum;Lee, Ho-Jae;Lee, Jun-Yong;Hong, Sang-Jeen
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.436-437
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    • 2012
  • Double patterning technology (DPT) has been suggested as a promising candidates of the next generation lithography technology in FLASH and DRAM manufacturing in sub-40nm technology node. DPT enables to overcome the physical limitation of optical lithography, and it is expected to be continued as long as e-beam lithography takes place in manufacturing. Several different processes for DPT are currently available in practice, and they are litho-litho-etch (LLE), litho-etch-litho-etch (LELE), litho-freeze-litho-etch (LFLE), and self-aligned double patterning (SADP) [1]. The self-aligned approach is regarded as more suitable for mass production, but it requires precise control of sidewall space etch profile for the exact definition of hard mask layer. In this paper, we propose etch end point detection (EPD) in spacer etching to precisely control sidewall profile in SADP. Conventional etch EPD notify the end point after or on-set of a layer being etched is removed, but the EPD in spacer etch should land-off exactly after surface removal while the spacer is still remained. Precise control of real-time in-situ EPD may help to control the size of spacer to realize desired pattern geometry. To demonstrate the capability of spacer-etch EPD, we fabricated metal line structure on silicon dioxide layer and spacer deposition layer with silicon nitride. While blanket etch of the spacer layer takes place in inductively coupled plasma-reactive ion etching (ICP-RIE), in-situ monitoring of plasma chemistry is performed using optical emission spectroscopy (OES), and the acquired data is stored in a local computer. Through offline analysis of the acquired OES data with respect to etch gas and by-product chemistry, a representative EPD time traces signal is derived. We found that the SE-EPD is useful for precise control of spacer etching in DPT, and we are continuously developing real-time SE-EPD methodology employing cumulative sum (CUSUM) control chart [2].

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MOCVD 법에 의한 Ruthenium 박막의 증착 및 특성 분석

  • 강상열;최국현;이석규;황철성;석창길;김형준
    • Proceedings of the Korean Vacuum Society Conference
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    • 1999.07a
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    • pp.152-152
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    • 1999
  • 1Gb급 이상 기억소자의 캐패시터 재료로 주목받고 있는 (Ba,Sr)TiO3 [BST] 박막의 전극재료로는 Pt, Ru, Ir과 같은 금속전극과 RuO2, IrO2와 산화물 전도체가 유망한 것으로 알려져 있다. 그런데, DRAM의 집적도가 증가하게 되면, BST같은 고유전율 박막을 유전재료로 사용한다 하더라도, 3차원적인 구조가 불가피하게 때문에 기존의 sputtering 방법으로는 우수한 단차피복성을 얻기 힘들므로, MOCVD법이 필수적이다. 본 연구에서는 기존에 연구되었던 Pt에 비해 식각특성이 우수하고, 비교적 낮은 비저항을 갖는 Ru 박막증착에 대한 연구를 행하였다. 본 연구에서는 수직형의 반응기와 저항 가열 방식의 susceptor로 구성된 저압 유기금속 화학증착기를 사용하여 최대 6inch 직경을 갖는 기판 위에 Ru박막을 증착하였다. Precursor로는 기존에 연구된 적이 없는 bis-(ethyo-$\pi$-cyclopentadienyl)Ru (Ru(C5H4C2H5)2, [Ru(EtCp)2])를 사용하였으며, bubbler의 온도는 85$^{\circ}C$로 하였다. Si, SiO2/Si를 사용하였으며, 증착온도 25$0^{\circ}C$~40$0^{\circ}C$, 증착압력 3Torr의 조건에서 Ru 박막을 증착하였다. Presursor를 운반하는 수송기체로는 Ar을 사용하였으며, carbon과 같은 불순물의 제거를 위해 O2를 첨가하였다. 증착된 박막은 XRD, SEM, 4-point probe등을 통해 구조적, 전기적 특성을 평가하였으며, 열역학 계산을 위해서는 SOLGASMIX-PV프로그램을 사용하였다. Ru 박막의 증착에 있어서 산소의 첨가는 필수적이었으며, Ru 박막의 증착속도는 30$0^{\circ}C$~40$0^{\circ}C$의 온도 영역에서 200$\AA$/min으로 일정하였으며, 첨가된 산소의 양이 적을수록 더 치밀하고 평탄한 표면형상을 보였으며, 또한 더 낮은 전기 전도도를 보였다. 그리고 증착된 박막은 12~15$\mu$$\Omega$cm 정도의 낮은 비저항 값을 나타냈으며 이것은 기존의 sputtering 법에 의해 증착된 Ru 박막의 비저항 값들과 비교될만하다. 한편, 높은 온도, 높은 산소분압 조건에서 RuO2의 형성을 관찰하였으며, 이것은 열역학적인 계산을 통해서 잘 설명할 수 있었다.

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A Study on the Abnormal Oxidation of Stacked Capacitor due to Underlayer Dependent Nitride Deposition (질화막 성장의 하지의존성에 따른 적층캐패시터의 이상산화에 관한 연구)

  • 정양희
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.11 no.1
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    • pp.33-40
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    • 1998
  • The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

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Investiagtions on the Etching of Platinum Film using High Density Inductively Coupled Ar/Cl$_2$ HBr Plasmas

  • Kim, Nam-Hoon;Chang-Il kim;Chang, Eui-Goo;Kwon, Kwang-Ho
    • Transactions on Electrical and Electronic Materials
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    • v.1 no.3
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    • pp.14-17
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    • 2000
  • Giga bit dynamic random access memory(DRAM) requires the capacitor of high dielectric films. Some metal oxides films have been proposed as the dielectric material . And Pt is one of the most promising electrode materials. However very little has been done in developing the etching technologoy Pt film. Therefore, it is the first priority to develop the technology for plasma etching of Pt film. In this study, the dry etching of Pt film was investigated in Inductively Coupled Plasma(ICP) etching system with Cl$_2$/Ar and HBr/Cl$_2$/Ar gas mixing. X-ray photoelectron spectroscopy (XPS) was used in analysis of sidewall residues for the understanding of etching mechanism. We found the etch residues on the pattern sidewall is mainly Pt-Pt, Pt-Cl and Pt-Br compounds, Etch profile was observed by Scanning Electron Spectroscopy(SEM) . The etch rate of Pt film at 10%, Cl$_2$/90% Ar gas mixing ration was higher than at 100%. Ar. Addition of HBr to Cl$_2$/Ar as an etching gas led to generally higher selectivity to SiO$_2$. And the etch residues were reduced at 5% HBr/5% Cl$_2$/90% Ar gas mixing ration. These pages provide you with an examples of the layout and style which we wish you to adopt during the preparation of your paper, Make the width of abstract to be 14cm.

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자화 유도 결합 플라즈마의 산화물 건식 식각 특성에 관한 연구

  • Jeong, Hui-Un;Kim, Hyeok;Lee, U-Hyeon;Kim, Ji-Won;Hwang, Gi-Ung
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.08a
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    • pp.230-230
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    • 2013
  • 플라즈마를 활용한 미세 패턴의 건식 식각은 반도체 소자 공정에 있어서 가장 중요한 기술 중 하나이다. 한편, 매년 발행되는 ITRS Roadmap 에 따르면 DRAM 의 1/2 pitch 는 감소하는 동시에 Contact A/R (Aspect Ratio) 는 증가하고 있다. 이러한 추세 속에서 기존의 공정을 그대로 활용할 경우 식각물의 프로파일 왜곡 혹은 휨 현상이 발생하고 식각 속도가 저하되며 이러한 특성들이 결과적으로는 생산성의 저하로 이어질 수 있다. 이러한 현상을 최소화하기 위해서는 무엇보다 독립된 plasma parameter 들이 식각물의 프로파일 혹은 식각 속도 등에 어떠한 영향을 주는 지에 대한 학문적 이해가 필요하다. 본 논문에서는 최소 CD (Critical Dimenstion) 100nm, 최대 A/R 30 인 HARC (High Aspect Ration Contact hole) 의 식각 특성이 plasma parameter 에 따라 어떻게 변하는지 확인해 보고자 한다. 산화물의 식각은 대표적인 high density plasma source 중의 하나인 ICP에서 진행하였으며 기존에 알려진 plasma parameter 에 더하여 자장의 인가가 산화물의 식각 특성에 어떠한 영향을 주는지 살펴보고자 전자석을 ICP 에 추가로 설치하여 실험을 진행하였다. 결과적으로, plasma parameter 에 따른 혹은 자장의 세기 변화에 따른 산화물의 식각 실험을 플라즈마 진단 실험과 병행하여 진행함으로써 다양한 인자에 따른 산화물의 식각 메커니즘을 정확하게 이해하고자 하였다. 실험 내용을 요약하면 다음과 같다. 먼저, 전자석의 전류 인가 조건에 따라 축 방향 혹은 반경 방향으로의 자장의 분포가 달라질 수 있음을 확인하였고 플라즈마 진단 결과 축 방향 혹은 반경 방향으로의 자장이 증가하였을 때 고밀도의 플라즈마가 형성될 수 있음은 물론 반경 방향으로의 플라즈마 밀도의 균일도가 향상됨을 확인할 수 있었다. 또한 ICP 조건에서 바이어스 주파수, 압력, 바이어스 파워, 소스 파워, 가스 유량 등의 plasma parameter 가 산화물의 식각 특성에 미치는 영향 및 메커니즘을 규명하였고 이 과정을 통해 최적화된 프로파일을 바탕으로 축 방향 혹은 반경 방향으로 증가하는 자장을 인가하였을 때 (M-ICP 혹은 자화 유도 결합 플라즈마) ICP 대비 산화물의 식각 속도가 증가함은 물론 PR-to-oxide 의 선택비가 개선될 수 있음을 확인할 수 있었다. 자장의 인가에 따른 산화물의 정확한 식각 메커니즘은 향후의 실험 진행을 통해 이해하고 이를 통해 궁극적으로는 산화물의 식각 공정이 나아가야 할 올바른 방향을 제시하고자 한다.

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A Study on the Labor Change in Mountainous Villages (산촌(山村)의 노동력(勞動力) 변화(變化)에 관(關)한 연구(硏究))

  • Yo, Byoung Il;Park, Myoung Kyu
    • Journal of Korean Society of Forest Science
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    • v.45 no.1
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    • pp.37-45
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    • 1979
  • The purpose of the study was to define the labor change in the moutainous villages, So this study analyzed the mass dram of the population from the mountainous villages created by the unequal development between the first and second under the high economic development and the large difference in the income between city and rural area. The content of the study was (1) the foundation of the production in the survey area (2) labor change in the mountainous villages (3) the supply and the demand of the labor in this area. The date were collected from 118 household of 2 villages (one with a high level of brest product, and the other with a low level of forest products) in Cheon-nam Province through a questionarie. The results of the study were as follows. 1. The mass drain in the mountainous villages started in the middle of 1970's, and the rate of drain has been very rapid and accelerated. 2. The drain of the mountainous village with a low level of forest products is more than that of the mountainous village with a high level of forest products. 3. In the mountainous village with high level of forest products, the specialization in the farmer class has begun and the farmers with a side job are now increasing. 4. Generally the major drain consisted of the young class (16-30 age), and consequently it caused a change in the composition of labor power into old age and women. 5. The character of the forest labor market is how changing from closed to open.

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