• Korean Journal of Materials Research
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• v.9 no.6
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• pp.604-608
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• 1999

Semiconductor industry requires the development of new technology such as 300 mm technology, suitable for manufacturing the next generation dervices. A promising process for realizing 300 mm technology can be achieved by using enlarged microwave plasma chemical vapor deposition (MWCVD) technology. In this work, we used radial line slot antenna for enlarging microwave plasma area, and carried ut the deposition of polysilicon films using enlarged MWCVD for the first time in Korea. The results was as follows. Deposited polysilicon films showed various degrees of crystallinity as well as epitaxy to silicon substrates even at low temperature of $300^{\circ}C$. Deposition rates also controled crystallization behavior and slo deposition rates showed very high crystallinity. It could be said that enlarged MWCVD system and technology was worth to get attraction as one os future technologies for 1 G DRAM era.

• Journal of the Korea Society of Computer and Information
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• v.24 no.7
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• pp.1-8
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• 2019

Recently, an SSD with hybrid buffer memories is actively researching to reduce the overall latency in server computing systems. However, existing hybrid buffer policies caused many swapping operations in pages because it did not consider the overall latency such as read/write operations of flash chips in the SSD. This paper proposes the clock with hybrid buffer memories (CLOCK-HBM) for a new hybrid buffer policy in the SSD with server computing systems. The CLOCK-HBM constructs new policies based on unique characteristics in both DRAM buffer and NVMs buffer for reducing the number of swapping operations in the SSD. In experimental results, the CLOCK-HBM reduced the number of swapping operations in the SSD by 43.5% on average, compared with LRU, CLOCK, and CLOCK-DNV.

• Proceedings of the Korean Society of Computer Information Conference
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• 2020.01a
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• pp.1-2
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• 2020

응용프로그램의 응답성을 향상시키기 위해서는 저장장치 시스템의 데이터 처리 능력이 중요하다. 한편, 차세대 메모리(NVDIMM)는 DRAM과 SSD 중간 정도의 성능 특성과 저장 용량을 갖는다. NVDIMM을 저장장치의 캐시로 사용함으로써 메모리와 저장장치의 격차는 많이 줄게 된다. 본 논문에서는 경량의 재사용 거리 측정 기법을 이용하여 효율적으로 디스크를 캐싱하는 기법을 제안한다. 제안 기법은 경량의 재사용 거리 측정 기법을 바탕으로 계산된 CFD(Computational Fluid Dynamics)값에 따라 디스크 캐시에 해당 데이터 적재 여부를 결정한다. 결과적으로 제안 기법을 적용한 디스크 캐시를 운용함에 따라 캐시의 히트율을 향상시켰다.

• Transactions on Electrical and Electronic Materials
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• v.1 no.4
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• pp.30-39
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• 2000

The variation of electrical properties of (Ba, Sr)TiO$_3$[BST] thin films deposited of RuO$_2$electrode with (Ba+Sr)/Tr ration was investigated. BST thin films with various (Ba+Sr)/Tr ration were deposited on RuO$_2$/Si substrates using in-situ RF magnetron sputtering. It was found that the electrical properties of BST films depends on the composition in the film. The dielectric constant of the BST films is about 190 at the (Ba+Sr)/Tr ration of 1.0, 1,025 and does not change markedly. But , the dielectric constant degraded to 145 as the (Ba+Sr)/Tr ratio increase to 1.0. In particular, the leakage current mechanism of the films shows the strong dependence on the (Ba+Sr)/Tr ration in the films. At the ration (Ba+Sr)/Tr=1,025, the Al/BST/RuO$_2$ capacitor show the most asymmetric behavior in the leakage current density, vs, electric field plot. It is considered that the leakage current of the (Ba+Sr)/Tr=1,025 thin films is controlled by the battier-Iimited process, i,e, Schottky emission.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.8-18
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• 2007

In this paper, a 4bit cell way structure of PoRAM and the sensing method to drive this structure are researched. PoRAM has a different operation from existing SRAM and DRAM. The operation is that when certain voltage is applied between top electrode and bottom electrode of PoRAM device we can classify the cell state by measuring cell current which is made by changing resistance of the cell. In the decoder selected by new-addressing method in the cell array, the row decoder is selected "High" and the column decoder is selected "Low" then certain current will flow to the bit-line. Because this current is detect, in order to make large enough current, the voltage sense amplifier is used. In this case, usually, 1-stage differential amplifier using current mirror is used. Furthermore, the detected value at the cell is current, so a diode connected NMOSFET, that is, a device resistor is used at the input port of the differential amplifier to converter current into voltage. Using this differential amplifier, we can classify the cell states, erase mode is "Low" and write mode is "High", by comparing the input value, Vin, that is a product of current value multiplied by resistor value with a reference voltage, Vref.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.24-32
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM(or SRAM) cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1)simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering, like smoothing and segmentation, may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.10
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• pp.811-816
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• 2012

The effect of co-sputtering condition on the structural properties of $Mg_xZn_{1-x}O$ thin films grown by RF magnetron co-sputtering system was investigated for manufacturing ZnO/MgZnO structure LED. $Mg_xZn_{1-x}O$ thin films were grown with ZnO and MgO target varying RF power. Structural properties were investigated by X-ray diffraction (XRD) and Energy dispersive spectroscopy (EDS). The ZnO thin films have sufficient crystallinity on the high RF power. As RF power of ZnO target increased, the contents of MgO in the $Mg_xZn_{1-x}O$ film decreased. LED was manufactured using ZnO/MgZnO multi-layer on p-GaN/$Al_2O_3$ substrate. Threshold voltage of multi-layer LED was appeared at 8 V, and it was luminesced at wave length of 550 nm.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.87-95
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• 1996

We have studied the effects of La concentration on the optical and electrical properties of lead lanthanum titanate (PLT) thin films by using sol-gel method. Both the optical and electrical properties are greatly affected by the La concentration. The refreactiv eindices of the films varied from 2.23 to 1.93 with varying La concentration in the range from 15 to 33 mol%. The dielectric constants of the films vary form 340 to 870 with varying La concentration in the range form 15 to 33 mol%. Hysteresis loop becomes slimmer with the increase of La concentration form 15 to 28mol% and little fatter again with the increase of La concentration form 28 to 33 mol%. Among the films investigated in this research, PLT(28) thin film shows the best dielectric properties for the application to the dielectrics of ULSI DRAM's. At the frequency of 100Hz, the dielectric constant and the loss tangent of PLT(28) thin films are 940 and 0.08 respectively. Its leakage current density at 1.5${\times}10^{5}$V/cm is 1${\times}10^{-6}A/cm^{2}$. The comparision between the simulated and the experimental curves for the switching transient characteristics shows that PLT (28) thin films behaves like normal dielectrics.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.99-99
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• 2000

본 논문에서는 RF Magnetron Sputtering 방법으로 Ba0.5Sr0.5TiO3 박막을 Pt/Ti/SiO2/Si 기판위에 증착하였다. Ar과 O2의 가스비는 90:10부터 50:50까지 O2의 함유비율을 10씩 증가시켰으며, 모든 조건에서 증착온도는 실온으로 설정하였다. Ba0.5Sr0.5TiO3 박막의 증착후 각 가스비에 따른 동일한 샘플에 대해 RTA(Rapid Thermal Anneal) 장비를 이용하여 $600^{\circ}C$에서 열처리는 하여 열처리 효과에 대한 특성도 조사하였다. 최종적으로 제작한 BST 커패시터는 Pt/BST/Pt 구조를 갖는 MIM(Metal-Insulator-Metal) 구조의 커패시터였으며 상.하부 전극은 전기적 특성이 우수한 Pt를 사용하였다. 제작된 BST 커패시터를 대해 유전 특성을 조사하기 위해 C-V 측정을 한 결과 산소 함유량이 증가함에 따라 유전율의 증가를 보여주었으며, 제작된 샘플 중 산소 함유량이 30인 샘플은 300이상의 우수한 유전율을 나타내었다. 또한 누설 전류특성에서는 모든 샘플에 대해 1.0V의 인가전압에서 1.0$\times$106A/cm2 이하의 누설 전류 밀도 값을 가져 전기적으로도 안정된 커패시터 구조임을 확인하였다. 또한 막의 증착상태와 미세구조관찰을 위해 SEM 측정을 하였고 구성성분 결정 구조를 알기 위해 XRD 측정도 시행하였다. 결과적으로 본 논문에서 제작된 커패시터 중 Sr/O의 비율이 70:30인 샘플이 가장 우수한 유전특성을 나타내었고, 이 샘플의 유전특성과 누설 전류 특성은 차세대 메모리인 1GigaByte급 DRAM에 적용 가능한 조건들을 만족시켰다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.1
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• pp.5-10
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• 2003

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.