• ETRI Journal
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• v.26 no.6
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• pp.583-588
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• 2004

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.329-337
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• 2001

It has been known that the leakage current in the low field region consists of the dielectric relaxation current and intrinsic leakage current, which cause the charge loss in dynamic random access memory (DRAM) storage capacitor using (Ba,Sr)TiO$_{3}$ (BST) thin film. Especially, the dielectric relaxation current should be seriously considered since its magnitude is much larger than that of the intrinsic leakage current in giga-bit DRAM operation voltage (~IY). In this study, thermally stimulated current (TSC) measurement was at first applied to investigate the activation energy of traps and relative evaluation of the density of traps according to process change. And, through comparing TSC to early methods of I-V or I-t measurement and analyzing, we identify the origin of the dielectric relaxation current and investigate the reliability of TSC measurement. First, the polarization condition such as electric field, time, temperature and heating rate was investigated for reliable TSC measurement. From the TSC measurement, the energy level of traps in the BST thin film has been investigated and evaluated to be 0.20($\pm$0.01) eV and 0.45($\pm$0.02) eV. Based on the TSC measurement results before and after rapid thermal annealing (RTA) process, oxygen vacancy is concluded to be the origin of the traps. TSC characteristics with thermal annealing in the MIM BST capacitor have shown the same trends with the current-voltage (I-V) and current-time (I-t) characteristics. This means that the TSC measurement is one of the effective methods to characterize the traps in the BST thin film.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.6
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• pp.44-51
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• 1999

The electrical conduction mechanism of high dielectric $(Ba,Sr)TiO_3$ (BST) thin film capacitor, which is the promising cell capacitor for high density DRAM, was investigated in low field region (<0.2MV/cm). It is known that the current in the low field region consists of dielectric relaxation current and leakage current. The current-time (I-t) measurement technique under the constant voltage was used for extracting successfully each current component. The conduction mechanism of the BST capacitor was deduced from the dependency of the current on the measurement temperature, strength of electric field, the polarity of applied electric field and post annealing process. From these results, it was suggested that the dielectric relaxation current and the leakage current are originated from the redistribution of internally trapped electron by hopping process and Pool-Frenkel conduction mechanism, respectively. It was also concluded that traps causing these two current components are due to oxygen vacancies within the BST film.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.76.2-76
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• 1998

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.17-17
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• 2001

고유전 (Ba, Sr)TiO₃ (BST) 박막을 이용한 DRAM storage capacitor의 저전계 영역에서의 전하손실을 발생시키는 커패시터의 누설전류는 유전완화전류와 진성 누설전류로 이루진다고 알려져 있다. 특히, 기가급 DRAM의 동작 전압(~IV)에서 유전완화전류가 진성 누설전류에 비해 훨씬 크기 때문에 이에 대한 심도 있는 연구가 필요하다. 본 연구에서는 thermally stimulated current (TSC) 측정법을 BST 박막에 처음으로 적용하여 트랩의 에너지 level 및 공정변화에 따른 트랩 밀도의 상대적 평가를 하였다. 그리고, 기존에 사용되던 전류-전압(I-V) 측정이나 전류-시간(I-t) 측정과 비교 및 분석함으로써 유전완화 전류의 원인을 규명하고 TSC 측정법의 신뢰성을 살펴보았다. 먼저 안정적인 TSC 측정을 위해 전계, 시간, 온도 및 승온속도에 따른 polarization condition을 알아보았다 이 조건을 이용한 TSC 측정으로부터 BST 박막에서의 트랩의 energy level이 0.20(±0.01) eV와 0.45(±0.02) eV임을 알 수 있었다. Rapid thermal annealing (RTA)을 이용한 후속 열처리에 따른 TSC 측정을 통하여 이 트랩들이 산소결핍(oxygen vacancy)에 기인함을 확인할 수 있었다. MIM BST 커패시터의 열처리에 대한 TSC 특성은 전류-전압(I-V) 및 전류-시간(I-t) 특성과 같은 경향성을 보인다. 이것은 TSC 측정이 BST 박막내의 트랩을 평가하는데 있어서 매우 효과적인 방법이라는 것을 보여준다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.78-85
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• 1995

We fabricated the Pb$_{1-0.28{\alpha}}La_{0.28}TiO_{3}$ (PLT(28)) thin film successfully by using the sol-gel method and characterized it to evaluate its potential for being utilized as the capacitor dielectrics of ULSI DRAMs. In our sol-gel process, the acetates were used as the starting materials. Through the TGA-DTA analysis, we established the excellent fabrication conditions of the sol-gel method for the PLT(28) thin film. We obtained the dense and crack-free PLT(28) thin film of 100% perovskite phase by drying at 350$^{\circ}C$ after each coating and final annealing at 650$^{\circ}C$. Its electrical properties were measured from the planar capacitors fabricated on the Pt/Ti/SiO$_{2}$/Si substrate. By the P-E hysteresis measurement, its paraelectric phase was identified and its dielectric constant and leakage current density were measured as 936 and 1.1${\mu}A/cm^{2}$, respectively. Those electrical values indicate that the PLT(28) thin film is the most successful candidate for the capacitor dielectrics of ULSI DRAMs at the present.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.4
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• pp.809-815
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• 2000

The box capacitor structure with HSG-Si described here reliably achieves a cell capacitance of 28fF with a cell area of a $0.4820\mum^2$ for 128Mbit DRAM. An HSG-Si formation technology with seeding method, which employs Si2H6 molecule irradiation and annealing, was applied for realizing 64Mbit and larger DRAMS. By using this technique, grain size controlled HSG-Si can be fabricated on in-situ phosphorous doped amorphous silicon electrodes. The HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors.The box capacitor structure with HSG-Si described here reliably achieves a cell capacitance of 28fF with a cell area of a $0.4820\mum^2$ for 128Mbit DRAM. An HSG-Si formation technology with seeding method, which employs Si2H6 molecule irradiation and annealing, was applied for realizing 64Mbit and larger DRAMS. By using this technique, grain size controlled HSG-Si can be fabricated on in-situ phosphorous doped amorphous silicon electrodes. The HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.784-787
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• 2002

We prepared the PLT(28) thin film by using sol-gel method and investigated the structure and electrical properties of the film. With the XRD and AFM analyses, it is found that PLT(28) thin film annealed at 6sot has a complete perovskite structure and its surface roughness is about 22$\AA$. We prepared PLT(28) thin film on the Pt/TiO$_{x}$SiO$_2$/Si substrate, in which the specimen has a planar capacitor structure, and analyzed the electrical properties of PLT(28) thin film. In result, PLT(28) thin film has a paraelectric phase and its dielectric constant and loss tangent at 10kHz are 761 and 0.024, respectively. Also, the storage charge density and leakage current density of PLT(28) thin film at W are 134fC/$\mu$m2 and 1.01 $\mu$A/cm2, respectively. As a result of this, we concluded that the PLT(28) thin film is a promising material to be used as a capacitor dielectrics for next generation DRAM.M.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.12
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• pp.1001-1007
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• 2001

In this study, high dielectric materials, (Pb,La)Ti $O_3$ thin films were fabricated by PLD (Pulsed Laser Deposition) method and investigated in terms of structural and electrical characteristics in order to develope the dielectric materials for the use of new capacitor layers of Giga bit-level DRAM. The deposition conditions were examined in order to fabricate uniform thin films through systematic changes of oxygen pressures and substrate temperature. The uniform thickness and smooth morphology of (P $b_{0.72}$L $a_{0.28}$)Ti $O_3$ thin films were obtained at the conditions of substrate-target distance 5.5[cm], laser energy density 2.1[J/$\textrm{cm}^2$], oxygen pressure 200[mTorr] and substrate temperature 500[$^{\circ}C$]. After the (P $b_{0.72}$L $a_{0.28}$)Ti $O_3$ thin films were fabricated under the above conditions, they were post-annealed by RTA process in order to increase the dielectric constant. The film thickness of 1200 [$\AA$] had dielectric constant 821. Assuming that operating voltage is 2V, leakage current density of (P $b_{0.72}$L $a_{0.28}$)Ti $O_3$ thin films would result into 10$^{-7}$ [A/$\textrm{cm}^2$] and satisfied the specification of 256M DRAM planar capacitor, 4$\times$10$^{-7}$ [A/$\textrm{cm}^2$]m}^2$]

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.6
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• pp.1128-1135
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• 2001

In this paper, a new HSG-Si formation technology, "seeding method', which employs Si$_2$H$_{6}$-molecule irradiation and annealing, was applied for realizing 64Mbit DRAMs. By using this technique, grain size controlled HSG-Si can be fabricated on in-situ phosphorous-doped amorphous-Si electrode. The new HSG-Si fabrication technology achieves twice the storage capacitance with high reliability for the stacked capacitors. In this technique, optimum process conditions of the phosphorous concentration, storage polysilicon deposition temperature and thickness of hemispherical grain silicon are in the range of 3.0-4.0E19atoms/㎤, 53$0^{\circ}C$ and 400$\AA$, respectively. In the 64M bit DRAM capacitor using optimum process conditions, limit thickness of dielectric nitride is about 65$\AA$.