• Electrical & Electronic Materials
• /
• v.3 no.3
• /
• pp.195-204
• /
• 1990

본 논문에서는 컴퓨터를 근본으로 한 Deep Level Transient Spectroscopy (DLTS) 장치를 구성하고 이를 이용하여 P형 Si MOS 캐패시터의 Si- $SiO_{2}$ 계면상태를 측정하여 트랩의 활성화에너지와 포획단면적 그리고 계면트랩밀도를 조사하였다. 실리콘 band gap내에 연속적으로 분포하고 있는 계면트랩을 상세히 고찰하기 위해 quiescent 전압의 위치를 변화시키면서 0.1volt의 미소한 펄스를 MOS에 주입하여 그 각각이 분리된 트랩이라고 생각되는 매우 좁은 에너지 영역에서 나오는 DLTS신호를 측정하였다. 또한 quiescent 전압의 위치, 주입펄스전압의 진폭 그리고 rate window의 선택이 DLTS 신호에 미치는 영향 등을 조사하였다. 측정결과, 계면트랩의 활성화에너지는 가전자대로 부터 0.16-0.45eV이고 포획단면적은 1.3*$10^{-19}$~3.2*$10^{-15}$$cm^{2}$, 계면트랩밀도는 1.8*$10^{10}$ ~ 2.5*$10^{11}$$cm^{-2}$e$V^{-1}$로 측정되었다.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.23 no.1
• /
• pp.120-125
• /
• 1986

Data analysis methods in lock-in amplifier based DLTS systems were discussed with regards to the signal-to-noise ratio and improvement of resolution of DLTS spectrum. The DLTS system based on wideband two-phase lock-in amplifier is shown to be the most preferabe for the studies in deep levels of low concentration. A single-temperature scanning DLTS methods in lock-in amplifier based system with the improved sensitivity is proposed. The method is tested on the characterization of deep levels in n-GaAs.

• Macromolecular Research
• /
• v.10 no.2
• /
• pp.75-79
• /
• 2002

Organic materials have considerable attention as active semiconductors for device applications such as thin-film transistors (TFTs) and diodes. Pentacene is a p-type organic semiconducting material investigated for TFTs. In this paper, we reported the morphological and electrical characteristics of pentacene TFT films. The pentacene transistors showed the mobility of 0.8 $\textrm{cm}^2$/Vs and the grains larger than 1 ${\mu}{\textrm}{m}$. Deep-level transient spectroscopy (DLTS) measurements were carried out on metal/insulator/organic semiconductor structure devices that had a depletion region at the insulator/organic-semiconductor interface. The duration of the capacitance transient in DLTS signals was several ten of seconds in the pentacene, which was longer than that of inorganic semiconductors such as Si. Based on the DLTS characteristics, the energy levels of hole and electron traps for the pentacene films were approximately 0.24, 1.08, and 0.31 eV above Ev, and 0.69 eV below Ec.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1995.11a
• /
• pp.23-24
• /
• 1995

기존의 웨이퍼 박막속에 절연박막이 삽입된 SOI(Silicon On Insulator) 웨이퍼 구조와 관련한 반도체 기판 재료가 커다른 관심을 끌어 왔으나, SOI 평가기술은 아직까지 체계적으로 확립된 것이 없으며, DLTS(Deep Level Transient Spectroscopy) 등을 이용한 전기적 평가는 거의 이루어지지 않은 상태이다. 본 연구에서는 직접접합된 웨이퍼를 약 10um내외의 활성화층을 형성시킨 6인치 P-형 SOI 웨이퍼를 제작하여 DLTS로 측정, 평가를 하였고, DLTS 측정후 관찰될 수 있는 에어지 트랩(Energy Trap)과 후속 열처리에서의 트랩의 변화등을 관찰하여, 후속 열처리조건에 따른 접합된 SOI 웨이퍼 계면의 안정화된 조건을 확보하였다.

• Proceedings of the KIEE Conference
• /
• 1989.11a
• /
• pp.83-86
• /
• 1989

Electrical conductivity, I - V and DLTS have been measured on polycrystalline samples of $\alpha-Fe_{2}O_{3}$ containing small deviation from stoichiometry and small amounts of added titanium. DLTS (Deep Level Transient Spectroscopy) in the current transient mode has been applied to the measurement of the trap density at the grain boundary. Titanium enters the $\alpha-Fe_{2}O_{3}$ lattice substitutionally as $Ti^{4+}$, thus producing an $Fe^{2+}$ and maintaining the average charge per cation at three. The $Fe^{2+}$acts as a donor center with respect to the surrounding $Fe^{3+}$ions.

• Korean Journal of Materials Research
• /
• v.11 no.1
• /
• pp.55-60
• /
• 2001

The effect of high energy B ion implantation and initial oxygen concentration upon defect formation and gettering of metallic impurities in Czochralski silicon wafer has been studied by applying DLTS( Deep Level Transient Spectroscopy), SIMS(Secondary ton Mass Spectroscopy), BMD (Bulk Micro-Defect) analysis and TEM(Transmission Electron Microscopy). DLTS results show the signal of the deep levels not only in as-implanted samples but also in low and high temperature annealed samples. Vacancy-related deep levels in as- implanted samples were changed to metallic impurities-related deep levels with increase of annealing temperature. In the case of high temperature anneal, by showing the lower deep level concentration with increase of initial oxygen concentration, high initial oxygen concentration seems to be more effective compared with the lower initial oxygen one.

• Electrical & Electronic Materials
• /
• v.9 no.7
• /
• pp.719-726
• /
• 1996

DLTS measurements were performed to study the annealing induced changes of the trap centers in MOV and to shed more light on the stability mechanism of the MOV. Two electron traps, Ec-0.26[eV] and Ec-(O.2-0.3)[eV], were observed in the unannealed samples in large quantities(7-9 X 1014[CM 3]), whereas the three electron traps Ec-0.17 [eV], Ec-0.26[eV] and Ec-(O.2-0.3)[eV] were observed far less in the annealed samples. The minima in the Ec-0.26[eV] trap density, coupled with the presented results that unannealed devices are unstable whereas 600.deg. C annealed devices are most stable, suggests that the instability of the MOV under long term electrical stressing is related to the Ec-0.26[eV] trap. This results support that the ion migration model for the device instability where the Ec-0.26[eV] defects may be the interstitial zinc or the migrating ions. The interstitial zinc originated as a result of the nonstoichiometric nature of ZnO might cause the degradation of the I-V characteristics of the MOV with long term electrical stressing.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07a
• /
• pp.150-153
• /
• 2004

본 논문에서는 780 nm 고출력 레이저 다이오드의 신뢰성을 향상시키기 위하여 DLTS(deep level transient spectroscopy)을 이용하여 MOCVD(metalorganic chemical vapor deposition) 성장 조건 변화에 따른 $Al_{0.48}Ga_{0.52}As$와 $Al_{0.1}Ga_{0.9}As$ 물질에서의 깊은준위(deep level)의 거동을 조사하였다. DLTS 측정결과, MOCVD로 성장된 막에서만 나타나는 결함(defect)으로 추정되는 trap A(0.3 eV), DX center로 알려진 trap B, 갈륨(Ga) vacancy와 산소(O2) 원자의 복합체(complex)에 의한 결함인 trap D(0.6 eV) 및 EL2 라고 불리우는 trap E(0.9 eV)의 네 가지 깊은준위들이 관측되었고, 성장 조건의 변화에 따라 깊은 준위들의 농도가 감소하는 것을 관측함으로써 최적 성장 조건을 찾을 수 있었다.

• Journal of IKEEE
• /
• v.26 no.2
• /
• pp.306-312
• /
• 2022

We investigated electrical properties and deep level traps in 4H-SiC merged PiN Schottky (MPS) diodes with different barrier heights by different PN ratios and metallization annealing temperatures. The barrier heights of MPS diodes were obtained in IV and CV characteristics. The leakage current increased with the lowering barrier height, resulting in 10 times larger current. Additionally, the deep level traps (Z_1/2 and RD_1/2) were revealed by deep level transient spectroscopy (DLTS) measurement in four MPS diodes. Based on DLTS results, the trap energy levels were found to be shallow level by 22~28% with lower barrier height It could confirm the dependence of the defect level and concentration determined by DLTS on the Schottky barrier height and may lead to incorrect results regarding deep level trap parameters with small barrier heights.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.460-460
• /
• 2013

본 연구는 Si (111) 기판위에 Ga 분자선량을 변화시켜 GaN 박막을 molecular beam epitaxy 법으로 성장하고, Schottky 장벽 다이오드를 제작한 후에 deep level transient spectroscopy (DLTS) 법을 통하여 깊은 준위 결함에 대하여 조사하였다. 성장 시 Ga 분자선량은, 그리고 Torr로 달리하여 V/III 비율을 변화시켰고, Schottky 장벽 다이오드 제작을 위하여 e-beam evaporator를 사용하여 metal을 증착하였다. Schottky 접촉에는 Ni (20 nm)/Au (100 nm)를 증착하였고, ohmic 접촉에는 Ti (20 nm)/Au (100 nm)를 증착하고 I-V, C-V 그리고 DLTS를 측정하였다. DLTS 신호를 통해 GaN 박막 성장 과정에서 형성되는 깊은 결함의 종류를 확인하였으며, 열처리 등의 처리 및 측정 조건변화에 따른 결함의 거동과 종류 및 원인에 대하여 분석 설명하였다.