• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.3
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• pp.74-80
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• 2012

Recently at SCIS2011, Nakatsu et. al. proposed multi-round Correlation Power Analysis(CPA) on Hardware Advanced Encryption Standard(AES) to improve the performance of CPA with limited number of traces. In this paper, we propose, Multi-Round CPA to retrieve master key using CPA of 1round and 2round on Hardware DES. From the simulation result for the proposed attack method, we could extract 56-bit master key using the 300 power traces of Hardware DES in DPA contes. And it was proved that we can search more master key using multi-round CPA than using single round CPA in limited environments.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.600-607
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• 2004

The paper describes the implementation of the video conferencing system using public key infrastructure which is used for user authentication and media stream encryption. Using public key infrastructure, we are able to reinforce the authentication for conference participant and block several malicious hacking while protecting conference control information. The paper shows the implementation of the transportation layer secure protocol in conformity with Korea public key authentication algorithm standard and symmetric key encryption algorithm (RC2, SEED, DES and 3DES) for media stream encryption. The feature of the paper is transportation layer secure protocol that is implemented for protection of information on a user authentication and video conference and the media streaming encryption algorithm also can be envisioned with another block encryption algorithm. The key for media streaming encryption may be safely distributed by the transportation layer secure protocol.

• Journal of Communications and Networks
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• v.12 no.4
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• pp.317-329
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• 2010

In recent years, many sparse estimation methods, also known as compressed sensing, have been developed. However, most of these methods presume that the measurement matrix is completely known. We develop a new blind maximum likelihood method-the expectation-sparse-maximization (ESpaM) algorithm-for models where the measurement matrix is the product of one unknown and one known matrix. This method is a variant of the expectation-maximization algorithm to deal with the resulting problem that the maximization step is no longer unique. The ESpaM algorithm is justified theoretically. We present as well numerical results for two concrete examples of blind channel identification in digital communications, a doubly-selective channel model and linear time invariant sparse channel model.

• The Transactions of the Korea Information Processing Society
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• v.4 no.6
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• pp.1565-1575
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• 1997

A new encryption algorithm had been proposed as a replacement to the Data Encryption Standard (DES) in [1,2]. It called the Extended DES (EDES) has a key length of 112 bits. The plaintext data consists of 96 bits divided into 3 sub-blocks of 32 bits each. The EDES has a potentially higher resistance to differential cryptanalysis that the DES due to the asymmetric number of f functions performed on each of the 3 sub-blocks and due to the increase of S-boxes from 8 to 16. This paper propose a hardware design for the EDES and its implementation in VLSI. The VLSI chip implements data encryption and decryption in a single hardware unit. With a system clock frequency of 15Mhz the device permits a data conversion rate of about 90Mbit/sec. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.852-855
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• 2005

This paper introduces a case study of designing a cryptographic processor dedicated to VPN/SSL system. The designed processor supports not only block cipher algorithm, including 3DES, AES, and SEED, but also 163 bit ECC public key crypto algorithm. Moreover, we adopted PCI Master interface in the design, which guarantees fast computation of cryptographic algorithm prevalent in general information security systems.

• Journal of the Korea Computer Industry Society
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• v.3 no.5
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• pp.595-604
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• 2002

In this paper, we designed the encryption algorithm which protects ciphertext from deciphering solve the problem that it can pass the incorrect meaning. The algorithm checks the error of ciphertext during deciphering, and then if there are some errors of more than one bit. It stops the deciphering sequence and it doesn't pass any contents to receiver by removing the deciphering contents which was already done. The experiment compared with DES algorithm that is representative algorithm of secret key. As the result of experiment, the part that error bit was included with was deciphered to one that was different from plaintext, but it showed 100% decipher_rate. by the algorithm showed decipher_rate of 0% with deciphering through the error check.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.4
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• pp.709-717
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• 2012

The round reduction on block cipher is a fault injection attack in which an attacker inserts temporary errors in cryptographic devices and extracts a secret key by reducing the number of operational round. In this paper, we proposed an improved round reduction method to retrieve master keys by injecting a fault during operation of loop statement in the Triple DES. Using laser fault injection experiment, we also verified that the proposed attack could be applied to a pure microprocessor ATmega 128 chip in which the Triple DES algorithm was implemented. Compared with previous attack method which is required 9 faulty-correct cipher text pairs and some exhaustive searches, the proposed one could extract three 56-bit secret keys with just 5 faulty cipher texts.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.333-337
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• 2006

Symmetric block ciper algorithm consists of a chains of operations such as permutation and substitution. There exists four kinds of operation mode, CBC, ECB, CFB, and OFB depending on the operation paradigm. Since the final ciper text is obtained through the many rounds of operations, it consumes much time. This paper proposes a pipelined design methodology which can improve the speed of crypto operations in ECB mode. Because the operations of the many rounds are concatenated in serial and executed concurrently, the overall computation time can be reduced significantly. The experimental result shows that the method can speed up the performance more than ten times.

• 한국디지털정책학회:학술대회논문집
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• 2004.11a
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• pp.221-229
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• 2004

This paper aims at developing communication module and application prcgram for client management module and developing database management module and managing wireless communication facilities for server systems. To construct these aims, we have adapted DES algorithm and researched on encrypting and decrypting module development applicable to SMS Security System and optimize module size and processing speed.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1997.11a
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• pp.205-213
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• 1997

본 논문에서는 암호화 알고리즘의 표준으로 자리잡은 DES(Data Encryption Standard) 알고리즘을 시스템 설계 기술언어인 VHDL을 이용하여 top-down 방식으로 설계하고 시뮬레이션을 수행하여 암ㆍ복호화의 결과를 보여준다. 또한 이것을 FPGA로 구현함으로써 하드웨어가 차지하는 면적과 속도를 산출 비교하여 암호화 속도 및 크기의 최적화를 위한 설계 방식을 제안한다. 본 논문에서는 최종적으로 V-system을 이용하여 시뮬레이션을 수행하고 Synopsys의 EDA 툴을 이용하여 합성을 한 후에 Xilinx사의 xdm을 이용하여 XC4025E에 칩으로 구현하였다.