• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.73.5-73
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• 2001

In this paper, we present a procedure to design the robust optimal supervisor which has the minimal cost in the sense of average for a given multiple-modelled discrete event system DES. In order to design the robust optimal supervisor, we extend the optimal supervisor design algorithm for a deterministic DES to the case of multiple-modelled DESs. In addition, using the proposed algorithm with modified costs of events and penalities of states, we can show whether a robust supervisor for a given multiple-modelled DES exists and design the minimally restricted robust supervisor.

• Journal of KIISE:Information Networking
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• v.29 no.6
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• pp.625-634
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• 2002

Cryptography is the methods of making and using secret writing that is necessary to keep messages private between two parties. Cryptography is compute-intensive algorithm and needs cpu resource excessively. To solve these problems, there exists hardware approach that implements cryptographic algorithm with hardware chip. In this paper, we presents the design and implementation of cryptographic hardware and compares its performance with software cryptographic algorithms. The experimental result shows that the hardware approach causes high I/O overheads when it transmits data between cryptographic board and host cpu. Hence, low complexity cryptographic algorithms such as DES does not improve the performance. But high complexity cryptographic algorithms such as Triple DES improve the performance with a high rate, roughly from two times to Sour times.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.2
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• pp.131-138
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• 2011

The previous FPGA cluster systems for a brute force search of DES keyspace have showed cost efficient performance, but the research on optimized implementation of the DES algorithm on a single FPGA has been insufficient. In this paper, the optimized DES implementation for a single FPGA of the commercial FPGA cluster system with 77 Xilinx Virtex5-LX50 FPGAs is proposed. Design space exploration using the number of pipeline stages in a DES core, the number of DES cores and the maximum clock frequency of a DES core is performed which leads to integrating 16 DES cores running at 333MHz. Also low power design is applied to reduce the loss of performance caused by limitation of power supply on each FPGA which results in fitting 8 DES cores running at 333MHz. When the proposed DES implementations would be used in the FPGA cluster system, it is estimated that the DES key would be found at most 2.03 days and 4.06 days respectively.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2003.12a
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• pp.77-85
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• 2003

기 상용화되고 있는 소프트웨어/하드웨어 제품의 복제방지에 대한 강도가 부족하여 쉽게 락이 크랙될 뿐 아니라 복제방지의 기능을 수행할 수 없는 단점을 보안하여 본 논문은 세계적으로 가장 많이 사용하고 있는 암호알고리즘 중의 하나인 DES를 구조적으로 수정하고 키 길이를 확장하여 암호학적 강도를 개선한 E-DES(Extended DES)를 설계하고, 이를 하드웨어로 구현하기 위해서 시스템 설계 기술언어인 VHDL로 코딩하고, FPGA를 이용, test chip을 구현하여 성능테스트를 수행한 다음, 설계된 FPGA 칩을 ASIC으로 제작하여 강력한 암호알고리즘을 가진 보안칩을 설계한다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.8 no.3
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• pp.17-26
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• 1998

본 논문에서는 DES(Data EncryptionStandard)시스템에서의 핵심부분에 해당되는f 함수에 대한 비선형 해석을 다룬다. 먼저 S-box의 입출력 형태를 비션형 결합함수 형태로 구성하여 f 함수에 대한 또 다른 형태의 분석방식을 제시한다. 이러한 분석방법은 DES뿐만 아니라 블록 암호시스템의 안전성 문제를 분석할 수 있으며, 또한 보다 안전한 블록암호 시스템을 제안하기 위한 기초자료로 사용될수 있을 것이다.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.169-172
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• 2000

This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.6 no.4
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• pp.85-96
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• 1996

In this paper, a simple method to increase securities of DES against DC and LC will be proposed. Our implementation results that the proposed algorithm is as fast as DES.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.674-677
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• 2003

Modern society is information-oriented society that allow letters in electron, telecommunication, computer, highly Information-Communication and information processing by great development of semi-conductor technologies. All businesses are depending on computer. Also, Great many user according to development who is worth watching eagerly of computer network and utilization of database and technology could collect, search, handle, transmit and store data at the same time using computer. But, while processing and use of information that use computer become convenient, exposure of data became serious relatively. For these reason, Security problem of data that need the secret rose. Accordingly, new encryption methods to use computer for security of data are presented and are developed continuously. Studied about DES, 3DES, RSA, ECC algorithm to select cipher algorithm to use in research hereafter in this treatise.

• Journal of the Korean School Mathematics Society
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• v.6 no.2
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• pp.101-115
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• 2003

DES is a very simple crytosystem that uses only permutation in mathematics. Recently AES is standardized based on DES. In this paper we introduce DES and its implementation. In particular, we tried to process Hangul in DES. This paper may be used in school mathematics education.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.5 no.1
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• pp.25-36
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• 1995

Differential Cryptanalysis(DC) and Linear Cryptanalysis(LC) are considered to be efficient attack methods which could be applied to DES and other DES-like private key Cryptosystems. This paper analyzes the DC and LC attack to DES and design a 80-bit block Cipher (80-DES) which could be strong against DC and LC Attack.