• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.3
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• pp.45-53
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• 2019

Moving image sharing technology has developed various servers and programs for personal broadcasting. In this paper, we propose the method of transmitting the multiple moving image, including the output channel of external streaming server. It also implements and tests multiple real-time broadcast channel automatic transmission systems that assign multiple output channels to automatic output channels. As a result of the experiment, it is easy to allocate moving image to broadcast channels that are output through the external streaming server's output channels regardless of the size of the streaming server, enabling the management of efficient output channels at the time of transmission of multiple moving image. The moving image can be provided through streaming method regardless of the type of moving image from the moving image provider terminal, and the moving image transmission can be controlled in various ways, including adding and changing channels for which the moving image is sent, and sending delayed to the moving image.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.6
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• pp.577-583
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• 2011

Radar performance test is one of the major steps for radar system design. However, it is restricted by time and cost when radar performance tests are performed with opportunity targets. So various simulated target generators are developed and used to evaluate radar performance. To simulate the target's range, most of simulated target generators are developed with optical line or DRFM(Digital RF Memory) technique but there are many restrictions such as limit of range imitation and test scenario because of their original usage. In this paper, DDL(Digital Delay Line) module for development of simulated target generator is designed with precise range simulation and easily embodiment feature. And pulse recognition and delay gap detection technique are used to simulate the time delay without distortions. Developed DDL module performances are verified through their performance tests and test results are described in this paper.

• Journal of the Optical Society of Korea
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• v.18 no.4
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• pp.406-413
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• 2014

An optical true-time delay beam-forming system using a tunable dispersion compensating module (DCM) for dense-wavelength division modulation (DWDM) and a multiwavelength fiber ring laser for a phased array antenna is proposed. The multiwavelength fiber ring laser has one output that includes four wavelengths; and four outputs that include only single-wavelength. The advantage of such a multiwavelength fiber ring laser is that it minimizes the number of devices in the phased array antenna system. The time delays according to wavelengths, which are assigned for each antenna element, are obtained from the tunable DCM. The tunable DCM based on a temperature adjustable Fabry-Perot etalon is used. As an experimental result, a DCM could be used to obtain the change of the beam angle by adjusting the dispersion value of the DCM at the fixed lasing wavelengths of the fiber ring laser in the proposed optical true-time delay.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1571-1576
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• 2005

DCS has many processing components and various communication elements. And its communication delay characteristic is affected diverse operating situation and context. Especially, binding signal which traversed from one control-node to another control-node undergo all sort of delay conditions. So its delay value has large deviation with the lapse of time, and the measurement of delay statistics during long time is very difficult by using general oscilloscope or other normal instruments. This thesis introduces the design and implementation of PC-based BDAS(Binding Delay Analysis System) System developed to overcomes these hardships. The system has signal-generator, IO-card, data-acquisition module, delay-calculation and analyzer module, those are implemented on industrial standard PC/Ethernet hardware and Windows/Linux platforms. This system can detect accurate whole-system-wide delay time including io, control processing and network delay, in the resolution of msec unit, and can analyze each channel's delay-historic data which is maintained by realtime database. So, this system has strong points of open system architecture, for example, user-friendly environment, low cost, high compatibility, simplicity of maintenance and high extension ability. Of all things, the measuring capability of long-time delay-statistics obtained through historic-DB make the system more valuable and useful, which function is essential to analyze accurate delay performance of DCS system. Using this system, the verification of delay performance of DCS for nuclear power plants is succeeded in KNICS(Korea Nuclear Instrumentation & Control System) projects

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1503-1513
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• 1998

This paper is related to a performance analysis of B-NT system, which is essential compositional equipment of B-ISDN access network. A simulator enabling performance analysis according to the change of network configuration topology and the change of user traffic is developed in this study. The developed B-NT, system simulator consists of graphic user interface module, simulation program automatic generator module, and B-NT system model library module. As examples of the results of performance analysis using the simulator, end-to-end user cell transmission delay time, queueing delay time in each system, and cell loss rate in the head node switch are presented. The simulator developed in this paper can be utilized in determining the network topology of B-NT system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.3
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• pp.570-576
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• 2004

In this paper, we design the IFFT/FFT (Inverse fast Fourier Transform/Fast Fourier Transform) modules for IEEE 802.11a-1999, which is a standard of the High-speed Wireless LAN using the OFDM (Orthogonal Frequency Division Multiplexing). The designed IFFT/FFT is the 64-point FFT to be compatible with IEEE 802.11a and the pipelined architecture which needs neither serial-to-parallel nor parallel-to-serial converter. We compare four types of IFFT/FFT modules for the hardware complexity and operation : R22SDF (Radix-2 Single-path Delay feedback), the R2SDF (Radix-2 Single-path Delay feedback), R2SDF (Radix-4 Single-path Delay Feedback), and R4SDC (Radix-4 Single-path Delay Commutator). In order to minimize the error, we design the IFFT/FFT module to operate with additional decimal parts after butterfly operation. In case of the R22SDF, the IFFT/FFT module has 44,747 gate counts excluding RAMs and the minimized error rate as compared with other types. And we know that the R22SDF has a small hardware structure as compared with other types.

• Journal of Communications and Networks
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• v.18 no.2
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• pp.201-209
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• 2016

In wireless sensor networks (WSNs) duty cycling has been an imperative choice to reduce idle listening but it introduces sleep delay. Thus, the conventional WSN medium access control protocols are bound by the energy-latency tradeoff. To break through the tradeoff, we propose a radio wave sensor called radio frequency (RF) wakeup sensor that is dedicated to sense the presence of a RF signal. The distinctive feature of our design is that the RF wakeup sensor can provide the same sensitivity but with two orders of magnitude less energy than the underlying RF module. With RF wakeup sensor a sensor node no longer requires duty cycling. Instead, it can maintain a sleep state until its RF wakeup sensor detects a communication signal. According to our analysis, the response time of the RF wakeup sensor is much shorter than the minimum transmission time of a typical communication module. Therefore, we apply duty cycling to the RF wakeup sensor to further reduce the energy consumption without performance degradation. We evaluate the circuital characteristics of our RF wakeup sensor design by using Advanced Design System 2009 simulator. The results show that RF wakeup sensor allows a sensor node to completely turn off their communication module by performing the around-the-clock carrier sensing while it consumes only 0.07% energy of an idle communication module.

• Journal of Power Electronics
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• v.11 no.3
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• pp.279-284
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• 2011

Network-based controls for ac motor drive systems are becoming increasingly important. In this paper, an ac motor control system is implemented by a motor control module and three sensor modules such as a voltage sensor module, a current sensor module, and an encoder module. There will inevitably be network time delays from the sensor modules to the motor control system, which often degrades and even destabilizes the motor drive system. As a result, it becomes very difficult to estimate the network delayed ac sensor data. An algorithm to reduce the effects of network time delays on sensor data is proposed, using both a synchronization signal and a simple method for estimating the sensor data. The algorithm is applied to a vector controlled induction motor drive system, and the performance of the proposed algorithm is verified with experiments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.10
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• pp.2605-2619
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• 1996

In this paper, we evaluated performance of mobile exchange control part. Queueing network model is used for modeling of mobile exchange control part. We developed a call control processing and location registration scenartio which has a message exchange function between processors in mobile exchange control part. A network symbol are used the simulation models that are composed of the initialization module, message generation module, message routing module, message processing module, message generation module, HIPC network processing module, output analysis module. as a result of computer simulation, we obtain the processor utilization, the mean queue length, the mean waiting time of control part based on call processing and location registration capacity. The call processing and location registration capacity is referred by thenumber of call attempts in the mobile exchange and must be satisfied with the quality of service(delay time).

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.180-187
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• 1996

This paper describes a post-layout simulation method using VHDL and C for verifying the architecture of antifuse-based FPGAs and the dedicated CAD system. An antifuse-based FPGA consists of programming circuitry including decoding logic, logic modules, segmented tracks, antifuses and I/O pads. The VHDL model which includes all these elements is used for logic verification and programming verification of the implemented circuit by reconstructing the logic circuit from the bit-stream generated from layout tool. The implemented circuit comprises of logic modules and routing networks. Since the routing delay of the complex networks is comparable to the delay of the logic module in the FPGA, the accurate post-layout simulation is essential to the FPGA system. In this paper, the C program calculates the delay of the routing netowrks using SPICE, elmore or horowitz delay models and the results feedback to the VHDL simulation. Critical path anc be found from this post-layout simulation results.