• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.871-874
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• 1999

We propose a low complexity M-D(multidimensional) TCM decoder VLSI architecture for ADSL System. We use the shared subset decoder module by modifying the whole decoding procedure. We reduce power consumption by using the MSA (modulo set area) operation, which removes multiplication in 4D metric calculation. Also the proposed TCM decoder reduces chip area. It can be adopted in high-speed xDSL system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 D
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• pp.3148-3150
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• 2000

Turbo codes that have attracted a great attention in recent years are applied to wireless communication networks that require variable quality of service and transmit over unknown fading channel. A MAP decoder is the constituent of turbo decoder. In this paper, we propose a high speed architecture of MAP decoder and a new normalization technique, In conclusion, this paper presents the efficient implementation of serial block MAP decoder for turbo codes.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.375-377
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• 2006

A Analog parallel processing-based Viterbi decoder which decodes PRML signal of DVD has been designed by CMOS circuit. The analog processing-based Viterbi decoder implements are functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The Analog parallel processing-based Viterbi decoding technology is applied for the PR(1,2,2,1) signal decoding of DVD. The benefits are low power consumption and less silicon consumption. In this paper, the comparison of the Analog parallel processing-based Viterbi Decoder which has a function of the error correction between Max operation and Average operation is discussed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.289-289
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• 2010

Translation Characteristics of Digital Decoder utilizing the analog parallel processing circuit technology is designed. The fast parallel viterbi decoder system acted by a replacement of the conventional digital viterbi Decoder has good propagation. we are applied proposed analog viterbi decoder to decode PR signal for DVD and analyze the specific circuit and signal characteristics.

• 대한전자공학회논문지
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• 제15권3호
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• pp.11-17
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• 1978

Medium scale 집적회로인 BCD to seven segment decoder/driver를 P-channel Metal-Oxide-Semiconductor집적회로 제작 기법으로 설계, 제작하였다. 본 소자는 특별히 common cathode seven segment light emitting diode에 적합하도록 설계되었다. decoder logic은 직렬로 연결된 두 개의 Read-Only-Memory로 구성되어 있으며 driver로는 channel이 넓은 FET를 사용하였다. 제작된 집적회로는 전원 전압이 -7 volt에서 -26 volt까지 변화할 때 정상적으로 동작하였으며 LED각 segment 전류의 non-uniformity는 약 ±10%이었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.465-472
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• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1939-1940
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• 2008

1967년 Andrew J. Viterbi에 의해 처음 제안된 Viterbi 알고리즘은 길쌈부호(convolution code)의 대표적인 복호방법으로 현재 통신 기술 중에서 가장 많이 쓰이는 것 중에 하나이다. Viterbi decoder는 사용되는 시스템의 사양에 따라 에러 수정 능력이 다른데 통신 channel 상의 오류뿐만 아니라 Viterbi decoder내부에 있는 메모리에서 발생하는 오류도 Viterbi decoder의 에러 수정 능력에 영향을 준다. 본 논문에서는 일반적으로 많이 확인되었던 channel상의 오류와 함께 Viterbi decoder내부에 있는 메모리에서 오류가 발생했을 때 복.부호기의 사양에 따른 에러정정능력을 분석하였다.

• 대한전기학회논문지:전력기술부문A
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• 제48권7호
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• pp.909-915
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• 1999

In this paper, we propose an efficient VLSI architecture of Reed-Solomon(RS) decoder. To improve the speed. we develope an architecture featuring parallel and pipelined processing. To implement the parallel and pipelined processing architecture, we analyze the RS decoding algorithm and the honor's algorithm for parallel processing and we also modified the Euclid's algorithm to apply the efficient parallel structure in RS decoder. To show the proposed architecture, the performance of the proposed RS decoder is compared to Shao's and we obtain the 10 % efficiency in area and three times faster in speed when it's compared to Shao's time domain decoder. In addition, we implemented the proposed RS decoder with Altera FPGA Flex10K-50.

• Journal of the Optical Society of Korea
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• 제20권3호
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• pp.335-342
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• 2016

We demonstrate an optical asynchronous transfer mode/wavelength division multiplexing (OATM/WDM) optical access network, using a router based on an optical header decoder to conduct next-generation communications. The router consists of a decoder or hardware analysis processing of the header bit and switches. The router in the OATM/WDM optical access network is a key technology by which to satisfy subscribers’ requests, including reliability, cost efficiency, high speed, large-capacity transmission, and elevated information security. In this study, we carry out experiments in which a header decoder delivers to 16 and 32 subscribers with a single wavelength in the router. These experiments confirm the decoder’s successful operation via hardware using 4 and 5 header bits. We propose that this system may significantly contribute toward the realization of an optical access network that provides high-quality service to subscribers of next-generation communications.

• 한국통신학회논문지
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• 제29권4C호
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• pp.448-453
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• 2004

기존의 QPSK와 TC-8PSK 신호를 복호할 수 있는 pragmatic TCM은 3bit 연판정을 적용한 Viterbi 복호기를 이용하기 위해서 sector phase quantizer가 필요하다. 이러한 단점을 보완하기 위해서 sector phase quantizer가 필요치 않고서 간단히 심볼 변환을 이용하여 연판정 출력이 가능한 새로운 알고리즘을 제안해서 이에 구조 및 성능을 분석하였으며 아울러 터보 부호에도 적용하였다. 성능 분석 결과, 기존의 pragmatic TCM에 비해 Euclidean 거리의 증가로 약 1［㏈］의 성능 향상을 가져옴을 알 수 있다.