• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.140-148
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• 2013

This paper presents a iterative Bose-Chaudhuri-hocquenghem (i-BCH) code and its high-speed decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed 6-iteration i-BCH code structure with interleaving method allows the decoder to achieve 9.34 dB net coding gain performance at $10^{-15}$ decoder output bit error rate to compensate for serious transmission quality degradation. The proposed high-speed i-BCH decoder architecture is synthesized using a 90-nm CMOS technology. It can operate at a clock frequency of 430 MHz and achieve a data processing rate of 100 Gb/s. Thus, it has potential applications in next generation forward error correction (FEC) schemes for 100 Gb/s optical communications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.104-111
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• 2002

In this paper, we proposed the architecture of the decoder which implements the multi-view images decoding algorithm. The study of the hardware structure of the multi-view image processing has not been accomplished. The proposed multi-view images decoder operates in a three stage pipelined manner and extracts the depth of the pixels of the decoded image every clock. The multi-view images decoder consists of three modules, Node selector which transfers the value of the nodes repeatedly and Depth Extractor which extracts the depth of each pixel from the four values of the nodes and Affine transformer which generates the projecting position on the image plane from the values of the pixels and the specified viewpoint. The proposed architecture is designed and simulated by the Max+plus II design tool and the operating frequency is 30MHz. The image can be constructed in a real time by the decoder with the proposed architecture.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.48-55
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• 2000

Recently due to rapid improvement of integrated circuit design environment, size of IC design is to become large to possible design System on Chip(SoC) that one chip with multi function enclosed. Also cause to this rapid change, consumption market is require to spend smallest time for new product development. In this paper to propose a methodology can design a large size IC for save time and applied to design of MPEG Layer 2 decoder to can use audio receiver in digital broadcast system. The digital broadcast audio decoder in this paper is pointed to save hardware size as optimizing algorithm. MPEG Layer 2 decoder algorithm is include MAC to can have an effect on hardware size. So coefficients are using sign digit expression. It is for hardware optimization. If using this method can design MAC without multiplier. The designed audio decoder is using 14,000 gates hardware size and save 22% (4000 gates) hardware usage than using multiplier. Also can design MPEG Layer 2 decoder usable digital broadcast receiver for short time.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.2
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• pp.53-64
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• 2011

In this paper, we propose a channel estimation of side information method based received motion vectors for distributed video coding. The proposed decoder estimates motion vectors of side information and transmits it to the encoder. As the proposed encoder generates side information which is the same to one in the decoder with received motion vectors, accuracy of side information of the decoder is assessed and it is transmitted to decoder. The proposed decoder can also estimate accurate crossover probability with received error information. As the proposed method conducts correct belief propagation, computational complexity of the channel decoder decreases and error correction capability is significantly improved with the smaller amount of parity bits. Experimental results show that the proposed algorithm is better in rate-distortion performance and it is faster than several conventional distributed video coding methods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.170-178
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• 2004

In this work a high speed 8-error correcting Reed-Solomon decoder is designed using the modified Euclid algorithm. Decoding algorithm of Reed-Solomon codes consists of four steps, those are, compute syndromes, find error-location polynomials, decide error-locations, and determine error values. The decoding speed is increased and the latency is reduced by using the parallel architecture in the syndrome generator and a faster clock speed in the modified Euclid algorithm block. In addition. the error locator polynomial in Chien search block is separated into even and odd terms to increase the overall speed of the decoder. All the functionalities of the decoder are verified first through C++ programs. Verilog is used for hardware description, and then the decoder is synthesized with a $.25{\mu}m$ CMOS TML library. The functionalities of the chip is also verified through test vectors. The clock speed of the chip is 250MHz, and the maximum data rate is 1Gbps.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2367-2372
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• 2015

One of various low-density parity-check(LDPC) codes that has been adopted in many communication standards due to its error correction ability is a quasi-cyclic LDPC(QC-LDPC) code, which leads to comparable decoder complexity. One of the main blocks in the QC-LCDC code decoder is a multi-size circular shifter(MSCS) that can perform various size rotation. The MSCS can be implemented with many structures, one of which is based on Banes network. The Benes network structure can perform the normal MSCS operation efficiently, but it cannot use the properties coming from specifications like rotation sizes. This paper proposesd a scheme where the Benes network structure can use the rotation size property with the modification of the control signal generation. The proposed scheme is applied to the MSCS of IEEE 802.16e WiMAX QC-LDPC decoder to reduce the number of MUXes and the critical path delay.

• The Journal of the Korea Contents Association
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• v.9 no.3
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• pp.9-19
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• 2009

In this paper, we propose a novel hardware architecture to facilitate the applicable SoC chip design of H.264/SVC which has a great deal of advancement in the international standardization in recent. Moreover, a new C-model simulator based on the proposed hardware system will be presented to support optimal SoC circuit development. Since the proposed SVC decoder is consist of some hardware engine for processing of major decoding tools and core processor for software processing, the system is simply implemented with the conventional embedded system. To improve the feasibility and applicability, and reduce the decoder complexity, the hardware decoder architecture is constructed with only the consideration of IPPP structure scalability without using the full B-picture. Finally, we present results of decoder hardware implementation and decoded picture to show the effectiveness of the proposed hardware architecture and C-model simulator.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.295-298
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• 2003

In this paper, a novel maximum a posterion (MAP) estimation for the channel decoding of H.264 codes in the presence of transmission error is presented. Arithmetic codes with a forbidden symbol and trellis search techniques are employed in order to estimate the best transmitted. And, there has been growing interest of communication, the research about transmission of exact data is increasing. Unlike the case of voice transmission, noise has a fatal effect on the image transmission. The reason is that video coding standards have used the variable length coding. So, only one bit error affects the all video data compressed before resynchronization. For reasons of that, channel needs the channel codec, which is robust to channel error. But, usual channel decoder corrects the error only by channel error probability. So, designing source codec and channel codec, Instead of separating them, it is tried to combine them jointly. And many researches used the information of source redundancy In received data. But, these methods do not match to the video coding standards, because video ceding standards use not only one symbol but also many symbols in same data sequence. In this thesis, We try to design combined source-channel codec that is compatible with video coding standards. This MAP decoder is proposed by adding semantic structure and semantic constraint of video coding standards to the method using redundancy of the MAP decoders proposed previously. Then, We get the better performance than usual channel coder's.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7C
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• pp.712-722
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• 2002

We have investigated a novel optical decoder for a fiber-optic code division multiple access(CDMA) communication systems. The conventional optical encoder and decoder have the advantage of simple structure. However the number of users in the system is limited by the auto- and cross-correlation properties generated in decoding process. In previous studies, to improve the system performance, although they used an optical code that minimize the sidelobe and cross-correlation, could not yet find a novel methods for performance improvement in fiber-optic CDMA system. Thus, it is necessary to investigate the novel optical decode in order to improve the performance of system. In this paper, we schematize the AND gate logic element(AGLE) composed with 1$\times$2 or 1$\times$3 coupler and the optical thyristor and propose the novel optical decoder using K(weight) AGLE. The optical thyristor only passes the overlapped signal and clips other signals. Such a novel concept means that the optical thyristor can operate as a hard-limiter. We analyze the fiber-optic CDMA system using the novel optical decoder with simulation and is found that the novel optical decoder using the AGLE and optical thyristor excludes the sidelobe and cross-correlation intensity between any two sequences.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2242-2250
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• 2009

Recently, with the advance of Ubiquitous era, the types of services become diverse. Especially, due to the rapid development of mobile technology, the new functions of mobile phones are added and the new applications of mobile phones are developed actively. Among the various applications related to mobile phones, 2 dimensional barcode-based applications are increasing. 2 dimensional barcode is mostly used for the management of past record. However, by combing 2 dimensional barcode with mobile phones, the application areas of 2 dimensional barcode are expanded to the means of publicity for education, tourism, and festivals. In this paper, we develop a QR code decoder running on smartphones, which connects on-line and off-line. In addition, we modify our decoder by detecting the point for performance enhancement based on TRIZ. We compare our decoder with an open-source based decoder in terms of the code size of decoding and the speed of decoding in order to prove that our decoder has a better performance than the other. Finally, we introduce two applications: u-map and u-pamphlet as QR code applications.