• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.24-31
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• 1998

This paper presents a pipeline high-level synthesis tool for designing trace-back systolic array viterbi decoder. It consists of a dta flow graph(DFG) generator and a pipeline data path synthesis tool. First, the DFG of the vitrebi decoder is generated in the from of VHDL netlist. The inputs to the DFG generator are parameters of the convolution encoder. Next, the pipeline scheduling and allocationare performed. The synthesis tool explores the design space efficiently, synthesizes various designs which meet the given constraints, and choose the best one.

• Journal of the Optical Society of Korea
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• v.9 no.3
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• pp.95-98
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• 2005

We propose a two-dimensional temporal/wavelength optical code division multiple access (OCDMA) encoder/decoder, which has an array of superstructured fiber Bragg gratings (SSFBGs). SSFBGs in an encoder/decoder have different wavelengths from each other and can be coded with the same OCDMA code or not. Simulation was performed to analyze the feasibility of the scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4A
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• pp.539-545
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• 2000

A 40-Mb/s, 64-state, R= 1/2, 3 bit soft decision Viterbi decoder based on Radix-4 method has been designed and fabricated using a FLEX10K CPLD chip in this paper. In order to implement the high-speed Viterbi decoder, the architectures of adder-compare-select(ACS), branch metric calculation(BMC), trace back(TB) are present. In practical designed by ASIC, the speed is faster than that of CPLD by 6~7 times. Therefore, 40 Mb/s Viterbi decoder architecture can be used for high-speed wireless multimedia communications with 200 Mb/s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.649-654
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• 2011

In this paper, we show new method to find number of errors in the Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square calculating circuit and parallel processing. The microcontroller of this Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

• ETRI Journal
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• v.30 no.1
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• pp.167-169
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• 2008

In this paper, we propose hardware architecture for a high-speed context-adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder, the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode $1920{\times}1088$ 30 fps video in real time at a 30.8 MHz clock.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.265-268
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• 2004

In this paper. we propose an adaptive step-size algorithm for the adaptive interference canceller (AIC) in the space-time trellis coded DS-CDMA system. In the AIC, the performance of the blind LMS algorithms that updates the tap-weight vector of the AIC is heavily dependent on the choice of step-size. To improve the performance of the fixed step-size AIC (FS-AIC), the regular adaptive step-size algorithm is extended in complex domain and applied to the joint AIC and ML decoder scheme. Simulation results show that the joint adaptive step-size AIC (AS-AIC) and ML decoder scheme using the proposed algorithm has boner performance than not only the conventional ML decoder but also the joint FS-AIC and ML decoder scheme without much increase of the decoding delay and complexity.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.131-136
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• 2005

UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MB-OFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MB-OFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.160-162
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• 2014

A programmable video decoding system with multi-core DSP and co-processors is presented. This system is adopted by Digital TV SoC (System on Chip) and is used for FHD HEVC (High Efficiency Video Coding) decoder. Using the DSP based programmable solution, we can reduce commercialization period by one year because we can parallelize algorithm development, software optimization and hardware design. In addition to the HEVC decoding, the proposed system can be used for other application such as other video decoding standard for multi-format decoder or video quality enhancement.

• Journal of Korea Society of Industrial Information Systems
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• v.11 no.4
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• pp.40-46
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• 2006

The performance of iterative multiuser detector and turbo decoder is presented to provide high quality multimedia services in WCDMA (wideband code division multiple access) system in this paper. Especially the relationship between the local iteration of turbo decoder and the global iteration of multiuser detector including the turbo decoder is analyzed. As a result, three local iterations and three global iterations are considered to be sufficient to provide satisfactory error performance with resonable complexity. The interference cancellation capability of global iteration is improved when the number of users is increased.

• MALSORI
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• no.64
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• pp.121-135
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• 2007

Speech signal is distorted by channel characteristics or additive noise and then the performances of speaker or speech recognition are severely degraded. To cope with the noise problem, we propose a modified HMM decoder algorithm using SNR-based observation confidence, which was successfully applied for GMM in speaker identification task. The modification is done by weighting observation probabilities with reliability values obtained from SNR. Also, we apply PSO (particle swarm optimization) method to the confidence function for maximizing the speaker identification performance. To evaluate our proposed method, we used the ETRI database for speaker recognition. The experimental results showed that the performance was definitely enhanced with the modified HMM decoder algorithm.