• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.285-288
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• 1998

Viterbi docoder is a maximum likelihood decoding method for convolution coding used in satellite and mobile communications. In this paper, a Viterbi decoder with constraint length of K=7, 3-soft decision and traceback depth of $\Gamma$=96 for convolution code is implemented using VHDL. The hardware size of designed decoder is reduced by 4 bit pre-traceback in the survivor memory.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.425-428
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• 1999

Turbo decoder were shown to achieve performance within 0.7㏈ of the Shannon capacity limit. This constituted a significant gain in power efficiency over other coding techniques known at the time. In this paper, Turbo code with constraint length K＝4, code rate 1/3, frame size 196bits(6 tail bits), 20㎳ frame and 6bit MAP decoder is implemented using VHDL. The designed Turbo code is used for voice service. Interactions of the system are used to attain large performance improvements.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.73-76
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• 1999

In this paper, we propose a new design of turbo decoder. It contains the simple additional unit which automatically decides the number of the iteration by detecting of the reliability value as threshold value. We investigate the relationship between the reliability value and the number of the iteration. We find the optimal threshold value without noticeable loss in performance. As a results of the simulation, it reduces the average number of the iteration compared with the conventional turbo decoder.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.99-102
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• 2002

In this work, we evaluated the performance of soft iterative decoder with soft block decoder in optical storage system. Because optical storage system requires run- length limited code in general, adaptation of the soft decoders such as turbo code or LDPC(low density parity check code) is difficult without soft block decoders. The performance of the overall optical detection system is evaluated and the simplified channel detection is also proposed.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.709-711
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• 1999

오늘날에 이르러 이동(mobile) 컴퓨팅의 중요성은 점차로 증가하는 추세에 있다. 하지만 이를 지원하기 위한 어플리케이션의 개발은 미진한 상태에 머물러 있으며, 특히 이동 컴퓨터를 위한 멀티미디어 서비스는 몇몇 기술적인 문제로 인하여 거의 제공도지 못하고 있는 것이 현실이다. 본 논문에서는 무선 LAN으로 구성된 이동 네트워크상에서 실시간 오디오 서비스를 제공하기 위한 MP3 Audio Decoder를 설계, 구현함으로써 이동 컴퓨팅 응용의 폭을 넓힌다. 그리고 이를 위한 몇 가지 고려사항과 관련 기술들을 서술하고, 구현된 프로그램의 실행 결과를 제시한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.6B
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• pp.727-735
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• 2001

본 논문은 8-VSB Advanced Digital TV용으로 사용할 수 있도록 ATSC(Advanced Television Standard Committee)의 규약을 만족시키도록 구현한 Reed Solomon 디코더에 대하여 기술한다. 구현된 RS Decoder는 공유된 Tree 구조의 Arithmetic 블록을 사용하여 종래의 기술보다 더 효율적인 연산기 구조를 제안하였으며 빠른 에러 탐지와 정정 시간으로 인한 FIFO의 사용갯수와 Latency Time을 크게 감소시킨 개선된 구조를 제안한다. 일반적으로 2N+A만큼의 Latency Time과 FIFO 개수를 N+A 만큼으로 감소시켰다. 이 RS 디코더는 Verilog HDL로 설계되었고 Synopsys Design Compiler에 의해 합성되었다.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.165-167
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• 1988

In this paper, the design of decoder for R-S code using discrete finite-field Fourier transform is presented. An important ingredient of this design is a modified Euclid algorithm for computing the error-locator polynomial. The computation of inverse elements is completely avoided in this modification of Euclid algorithm. This decoder is regular and simple, and naturally suitable for VLSI implementation.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.203-206
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• 1988

Direct Decoding Method for binary BCH codes which directly can find error location number from syndrome without calculating error locator polynomial is presented in this paper. The (255,239) BCH decoder is implemented using TTL logics. It is shown from our results that this decoder can be implemented with relatively simple hardware.

• Proceedings of the Acoustical Society of Korea Conference
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• 1991.06a
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• pp.78-81
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• 1991

Digital radio data is composed of groups which are divided into 4 blocks of 26 bits. And each block is made up of information word and check word. Check word of digital radio data that is composed ofcode word and offset word is used for group/block synchronization and error correction. In this paper, we have investigated the group/block synchronizer using offext word and shortened cyclic decoder for correcting error produced during the radio data transimission. Also, we have simulated the decoding process of the proposed decoder. From the simulation results, we have confirmed that the proposed decoder most with the required coding capcbility.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.355-356
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• 2006

MPEG-4 ER-BSAC decoder employes a full search method for maximum significance search and arithmetic decoding position search in spectral data decoding procedure. Then the search procedure have the most complexity. This paper proposes the new search method, the maximum significance tree structure, for the optimized implementation of BSAC decoder.