• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.7
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• pp.769-777
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• 2010

In this paper, a switchable circularly polarized microstrip patch antenna using PIN diodes and corner slots on ground plane is proposed at 2.4 GHz. The proposed antenna has a square microstrip patch and ground plane that consists of two pair of slots and PIN diodes. The electrical lengths of the slots are adjusted by using the switching characteristic of the PIN diode, so the polarization of the proposed antenna can be switchable between linear, left-handed(LH) and right-handed(RH). By separating the ground plane for the DC bias, the size reduction effect is also obtained. When the proposed antenna is operated as linear polarization, the return loss and impedance bandwidth are 15 dB, 59 MHz, and when operated as LH and RH polarization, the minimum axial ratio and 3-dB axial ratio bandwidth are 1.17 dB, 1.67 dB, 28 MHz, and 32 MHz, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.4
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• pp.91-96
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• 2020

The 33-mode dielectric and piezoelectric properties of Pb(In1/2Nb1/2)O3-Pb(Mg1/3Nb2/3)O3-PbTiO3 piezoelectric single crystals were measured under large electric field and compressive stress. The phase transition from the low temperature rhombohedral to the high temperature tetragonal structure was observed in the range of 110~140℃, and the Curie temperature changing to the cubic structure was about 165℃. The polarization change according to the compressive stress and electric field was measured. Relative dielectric constant was calculated from the slope of the polarization curve applied to the electric field, and the calculated relative dielectric constant increased as the applied stress increased, and the relative dielectric constant decreased as the applied electric field increased. The strain according to the compressive stress and electric field change was measured, the piezoelectric constant was calculated from the slope of the curve, and the phase transition according to the application of pressure was confirmed. In the case of practical application as an underwater or medical ultrasonic actuator, it is necessary to properly design the magnitude of the compressive stress applied to the device and the DC bias in order to maintain linear driving.

• Korean Journal of Materials Research
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• v.14 no.3
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• pp.203-210
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• 2004

Effects of various pretreatments on the adhesion of copper-coated polymer films were investigated. Copper-coated polymer films were prepared by an electron cyclotron resonance-metal organic chemical vapor deposition (ECR-MOCVD) coupled with a DC bias system at room temperature. PET(polyethylene terephthalate) film was employed as a substrate material and it was pretreated by industrially feasible methods such as chromic acid, sand-blasting, oxygen plasma and ion-implantation treatment. Surface characterization of the copper-coated polymer film was carried out by AFM(Atomic Force Microscopy) and FESEM(Field Emission Scanning Electron Microscopy). Surface energy was calculated by based on the value of the contact angle measured. The adhesion of copper/PET films was determined by a pull-off test according to ASTM D-5179. It was found that suitable pretreatment of the PET substrate was required for obtaining good adhesion property between copper films and the substrate. In this study the highest adhesion was observed in sand-blasting, and then followed by those of acid and oxygen plasma treatment. However, the effect of surface energy was insignificant in our experimental range. This is probably due to compensating the difference in surface energy from various pretreatments by exposing substrate to ECR plasma for 5 min or longer at the early stage of the copper deposition. Therefore, it can be concluded that surface roughness of the polymer substrate plays an important role to determine the adhesion of copper-coated polymer for the deposition of copper by ECR-MOCVD.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.67-67
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• 2009

Due to the scaling down of the dielectrics thickness, the leakage currents arising from electron tunneling through the dielectrics has become the major technical barrier. Thus, much works has focused on the development of high k dielectrics in both cases of memories and CMOS fields. Among the high-k materials, $Al_2O_3$ considered as good candidate has been attracting much attentions, which own some good properties as high dielectric constant k value (~9), a high bandgap (~2eV) and elevated crystallization temperature, etc. Due to the easy control of ion energy and flux, low ownership and simple structure of the inductively coupled plasma (ICP), we chose it for high-density plasma in our study. And the $BCl_3$ was included in the gas due to the effective extraction of oxygen in the form of BClxOy compound. In this study, the etch characteristic of ALD deposited $Al_2O_3$ thin film was investigated in $BCl_3/N_2$ plasma. The experiment were performed by comparing etch rates and selectivity of $Al_2O_3$ over $SiO_2$ as functions of the input plasma parameters such as gas mixing ratio, DC-bias voltage and RF power and process pressure. The maximum etch rate was obtained under 15 mTorr process perssure, 700 W RF power, $BCl_3$(6 sccm)/$N_2$(14 sccm) plasma, and the highest etch selectivity was 1.9. We used the x-ray photoelectron spectroscopy (XPS) to investigate the chemical reactions on the etched surface. The Auger electron spectroscopy (AES) was used for elemental analysis of etched surface.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.209-209
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• 2009

ITO 박막은 박막 태양전지, 유기 태양전지뿐만 아니라 유연한 디스플레이, 발광다이오드와 같은 광학적 장치에 투명한 전극으로써 널리 사용된다. 글라스나 플라스틱 기판위에 형성된 투명 전극은 식각을 통하여 전기회로를 구성한다. 또한 식각 특성을 개선할 필요가 있다. 이 연구에서 우리는 유리 기판위에 코팅된 ITO 박막을 유도결합 $BCl_3/Ar$ 플라즈마를 이용하여 식각하였다. ITO 박막은 RF 마그네트론 스퍼터링을 사용해 200 $^{\circ}C$에서 비알칼리 글라스 위에 증착하였고 ITO 박막의 총 두께는 약 250 nm 이었다. 또한 전기 전도성은 $4.483{\times}10^{-4}{\Omega}cm$, 캐리어 농도는 $3.923{\times}10^{20}cm^{-3}$이고, 홀 이동도는 $3.545{\times}10cm^{-2}/Vs$이었다. Ar 플라즈마에 $BCl_3$ 가스를 첨가시키면서 가스 비율에 따른 ITO의 식각 속도와 ITO와 PR과의 선택비를 측정하였다. 최대 식각 속도는 $BCl_3$(25%)/Ar(75%), 500 W의 RF power, -200 V의 DC-bias voltage, 그리고 2 pa의 공정압력일 때 588 nm/min이었고 선택비는 0.43으로 다소 낮게 측정되었다. 식각된 표면의 화학적 반응은 엑스선 광전자 분광법 (X-ray Photoelectron Spectroscopy)을 사용해 조사되었다. 그리고 식각된 표면의 거칠기는 원자현미경 (Atomic Force Microscopy)을 사용해 측정하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.104-104
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• 2009

Critical dimensions has rapidly shrunk to increase the degree of integration and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate insulator layer and the low conductivity characteristic of poly-silicon. To cover these faults, the study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$ and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-silicon gate is not compatible with high-k materials for gate-insulator. To integrate high-k gate dielectric materials in nano-scale devices, metal gate electrodes are expected to be used in the future. Currently, metal gate electrode materials like TiN, TaN, and WN are being widely studied for next-generation nano-scale devices. The TaN gate electrode for metal/high-k gate stack is compatible with high-k materials. According to this trend, the study about dry etching technology of the TaN film is needed. In this study, we investigated the etch mechanism of the TaN thin film in an inductively coupled plasma (ICP) system with $O_2/BCl_3/Ar$ gas chemistry. The etch rates and selectivities of TaN thin films were investigated in terms of the gas mixing ratio, the RF power, the DC-bias voltage, and the process pressure. The characteristics of the plasma were estimated using optical emission spectroscopy (OES). The surface reactions after etching were investigated using X-ray photoelectron spectroscopy (XPS) and auger electron spectroscopy (AES).

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.8
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• pp.1227-1234
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• 2013

An analog array with a 1.2 double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.10
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• pp.785-791
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• 2001

High dielectric (Ba, Sr) TiO$_3$ thin films were etched in an inductively coupled plasma (ICP) as a function of Cl$_2$/Ar mixing ration. Under Cl$_2$(20)/Ar(80), the maximum etch rate of the BST films was 400 $\AA$/mim and selectivities of BST to Pt and PR were obtained 0.4 and 0.2, respectively. Etching products were redeposited on the surface of BST and resulted in varying the nature of crystallinity. Therefore, we investigated the etched surface of BST by x-ray photoelectron spectroscopy (XPS) atomic force microscopy (AFM) and x-ray diffraction (XRD). From the result of XPS analysis, we found that residues of Ba-Cl and Ti-Cl bonds remained on the surface of the etched BST for high boiling point. The morphology of the etched surfact was analyzed by AFM. A smoothsurface(roughness ~2.8nm) ws observed under Cl$_2$(20)/Ar(80), rf power of 600 W, dc bias voltage of -250 V and pressure of 10 mTorr. This changed the nature of the crystallinity of BST. From the result of XRD analysis, the crystallinities of the etched BST film under Ar only and Cl$_2$(20)/Ar(80) were maintained as similar to as-deposited BST. However, intensity of BST(100) orientation under Cl$_2$ only plasma was abruptly decreased. This indicated that CI compounds were redeposited on the etched BST surface and resulted in changed of the crystallinity of BST during the etch process.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2001.06a
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• pp.14-14
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• 2001

Nitride films such as TiN, CrN etc. deposited on glass by PVD processes have been developed for many industrial applications. These nitride films deposited on glass were widely used for not only decorative and optical coatings but also wear and corrosion resistance coatings employed as dies and molds made of glass for the example of lens forming molds. However, the major problem of nitride coatings on glass by PVD process is non-uniform film owing to pin-hole and micro crack. It is estimated that nonuniform coating is influenced by a different surface energy between metal nitrides and glass due to binding states. In this work, therefore, for the evaluation of nucleation and growth mechanism of nitride films on glass TiN and CrN film were synthesized on glass with various nitrogen partial pressure by unbalanced magnetron sputtering. Prior to deposition, for the examination of relationship between surface energy and film microstructure plasma pre-treatment process was carried out with various argon to hydrogen flow rate and substrate bias voltage, duty cycle and frequency by using pulsed DC power supply. Surface energy owing to the different plasma pre-treatment was calculated by the measurement of wetting angle and surface conditions of glass were investigated by X-ray Photoelectron Spectroscopy(XPS) and Atomic Force Microscope(AFM). The microstructure change of nitride films on glass with increase of film thickness were analyzed by X-Ray Diffraction(XRD) and Scanning Electron Microscopy(SEM).

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1996.06a
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• pp.422-448
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• 1996

Low-temperature epitaxial growth of Si and SiGe layers of Si is one of the important processes for the fabrication of the high-speed Si-based heterostructure devices such as heterojunction bipolar transistors. Low-temperature growth ensures the abrupt compositional and doping concentration profiles for future novel devices. Especially in SiGe epitaxy, low-temperature growth is a prerequisite for two-dimensional growth mode for the growth of thin, uniform layers. UHV-ECRCVD is a new growth technique for Si and SiGe epilayers and it is possible to grow epilayers at even lower temperatures than conventional CVD's. SiH and GeH and dopant gases are dissociated by an ECR plasma in an ultrahigh vacuum growth chamber. In situ hydrogen plasma cleaning of the Si native oxide before the epitaxial growth is successfully developed in UHV-ECRCVD. Structural quality of the epilayers are examined by reflection high energy electron diffraction, transmission electron microscopy, Nomarski microscope and atomic force microscope. Device-quality Si and SiGe epilayers are successfully grown at temperatures lower than 600℃ after proper optimization of process parameters such as temperature, total pressure, partial pressures of input gases, plasma power, and substrate dc bias. Dopant incorporation and activation for B in Si and SiGe are studied by secondary ion mass spectrometry and spreading resistance profilometry. Silicon p-n homojunction diodes are fabricated from in situ doped Si layers. I-V characteristics of the diodes shows that the ideality factor is 1.2, implying that the low-temperature silicon epilayers grown by UHV-ECRCVD is truly of device-quality.