• Title/Summary/Keyword: DC characteristic

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Convergent Study of Aluminum Anodizing Method on the Thermal Fatigue (열 피로에 미치는 알루미늄 양극산화 제조방법의 융합연구)

  • Kang, Soo Young
    • Journal of the Korea Convergence Society
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    • v.7 no.5
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    • pp.169-173
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    • 2016
  • Anodic oxidation of aluminum has a sulfuric acid method and a oxalic acid method. Sulfuric acid concentration of the sulfuric acid method is 15~20 wt%. In the case of soft anodizing used in the $20{\sim}30^{\circ}C$ range, and voltage is the most used within a DC voltage 13~15V. In the case of hard anodizing used in the $0{\sim}-5^{\circ}C$ range. An aluminum oxide layer is made using sulfuric acid and oxalic acid. In this study, thermal fatigue of aluminum oxide layer which is made using sulfuric acid and oxalic acid is compared. Crack generating temperature of a sulfuric acid method and a oxalic acid method is $500^{\circ}C$ and $600^{\circ}C$. Thermal fatigue of aluminum oxide layer which is made using oxalic acid is better than thermal fatigue of aluminum oxide layer which is made using sulfuric acid. The characteristic of thermal fatigue can be explained by using thermal expansion coefficient of Al and Al2O3 and manufacturing temperature on Al anodizing. It was made possible through the convergent study to propose the manufacturing method of the anodic oxidation product used at a high temperature.

Characteristic of ITO-Ag-ITO multilayer thin films grown by linear facing target sputtering system (선형대향타겟 스퍼터로 성장시킨 ITO-Ag-ITO 다층박막의 특성 연구)

  • Jeong, Jin-A;Choi, Kwang-Hyuk;Lee, Jae-Young;Lee, Jung-Hwan;Bae, Hyo-Dae;Tak, Yoon-Heung;Ye, Min-Su;Kim, Han-Ki
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.66-66
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    • 2008
  • 본 연구에서는 ITO/Ag/ITO 다층 박막을 유기발광소자와 플렉시블 광전소자의 전극으로 적용하기 위하여 선형 대항 타겟 스퍼터(Linear facing target sputter) 시스템을 이용하여 성막하였고, ITO/Ag/ITO 다층박막의 전기적, 광학적, 구조적 특성을 분석하였다. 선형 대항 타겟 스퍼터 시스템은 강한 일방항의 자계와 타겟에 걸린 음극에 의해 전자의 회전, 왕복 운동이 가능해 마주보는 두 ITO 타겟 사이에 고밀도의 플라즈마를 구속 시켜 플라즈마 데미지 없이 산화물 박막을 성막시킬 수 있는 장치이다. 대항 타겟 스퍼터 시스템을 이용하여 성막한 ITO 전극을 DC power, working pressure, Ar/O2 ratio 에 따른 특성을 각각 분석하였다. glass 기판위에 최적화된 ITO 전극을 bottom layer로 두고, bottom ITO layer 위에 thermal evaporation 을 이용하여 Ag 박막을 6~20nm의 조건에 따라 두께를 다르게 성막하고, Ag 박막을 성막한 후에 다시 bottom ITO 전극과 같은 조건으로 ITO 전극을 top layer로 성막 하였다. 두 비정질의 ITO 전극 사이에 매우 앓은 Ag 박막을 성막 함으로 해서 glass 기판위에 ITO/Ag/ITO 다층 박막전극은 매우 낮은 저항과 높은 투과도를 나타낸다. ITO/Ag/ITO 박막의 전기적 광학적 특성을 보기 위해 hall measurement와 UV/visible spectrometer 분석을 각각 진행하였다. ITO/Ag/ITO 다층 박막 전극이 매우 얇은 두께임에도 불구하고 $4\Omega$/sq.의 낮은 면저항과 85%의 높은 투과도를 나타내는 이유는 ITO/Ag/ITO 전극 사이에 있는 Ag층의 표면 플라즈몬 공명 (SPR) 현상으로 설명할 수 있다. ITO/Ag/ITO 전극의 Ag의 거동을 분석 하기위해 FESEM분석과 synchrotron x-ray scattering 분석을 하였다. ITO/Ag/ITO 전극의 Ag층이 islands의 모양에서 연속적으로 연결되는 변화과정 중에 SPR현상이 일어남을 알 수 있다. 여기서, 대항 타겟 스퍼터 시스템을 이용하여 성막한 ITO/Ag/ITO 다층박막을 OLED 또는 inverted OLEDs의 top 전극으로의 적용 가능성을 보이고 있다.

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Design of a Low-Power CMOS Fractional-N Frequency Synthesizer for 2.4GHz ISM Band Applications (2.4GHz ISM 대역 응용을 위한 저전력 CMOS Fractional-N 주파수합성기 설계)

  • Oh, Kun-Chang;Kim, Kyung-Hwan;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.6
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    • pp.60-67
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    • 2008
  • A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.

Implementation of Analog Signal Processing ASIC for Vibratory Angular Velocity Detection Sensor (진동형 각속도 검출 센서를 위한 애널로그 신호처리 ASIC의 구현)

  • 김청월;이병렬;이상우;최준혁
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.4
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    • pp.65-73
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    • 2003
  • This paper presents the implementation of an analog signal-processing ASIS to detect an angular velocity signal from a vibrator angular velocity detection sensor. The output of the sensor to be charge appeared as the variation of the capacitance value in the structure of the sensor was detected using charge amplifiers and a self oscillation circuit for driving the sensor was implemented with a sinusoidal self oscillation circuit using the resonance characteristics of the sensor. Specially an automatic gain control circuit was utilized to prevent the deterioration of self-oscillation characteristics due to the external elements such as the characteristic variation of the sensor process and the temperature variation. The angular velocity signal, amplitude-mod)Hated in the operation characteristics of the sensor, was demodulated using a synchronous detection circuit. A switching multiplication circuit was used in the synchronous detection circuit to prevent the magnitude variation of detected signal caused by the amplitude variation of the carrier signal. The ASIC was designed and implemented using 0.5${\mu}{\textrm}{m}$ CMOS process. The chip size was 1.2mm x 1mm. In the experiment under the supply voltage of 3V, the ASIC consumed the supply current of 3.6mA and noise spectrum density from dc to 50Hz was in the range of -95 dBrms/√Hz and -100 dBrms/√Hz when the ASIC, coupled with the sensor, was in normal operation.

Electrochemical Characteristic on Lithium Intercalation into the Interface between Organic Electrolyte and Amorphous WO3 Thin Film Prepared by e-beam Evaporation Method (e-beam 증발법으로 제조된 비정질 WO3박막과 전해질 계면으로 삽입되는 리튬의 층간 반응에 관한 전기화학적 특성)

  • Min, Byoung-Chul;Sohn, Tae-Won;Ju, Jeh-Beck
    • Applied Chemistry for Engineering
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    • v.8 no.6
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    • pp.1022-1028
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    • 1997
  • This work was performed to study the characteristics of electrochemical intercalation reactions occurring at the interface between the organic electrolyte and tungsten trioxide thin film (thickness of $4000{\AA}$) prepared by e-beam evaporation method as cathodically coloring oxide with regard to the electrochromism by the intercalating reactions of the lithium cation in the 1M $LiClO_4/PC$ organic solution. The characteristics of electrochemical intercalation reactions were investigated by various DC electrochemical methods such as cathodic Tafel polarization test, multiple and the single sweep cyclic voltammetry and the coulomety titrations method. The surfaces of thin films were observed with the patterns of X ray diffraction after the coloring and bleaching reactions. In comparison with the previous results that $WO_3$ thin film intersely detached from the surface of electrode when the hydrogen cation was intercalated into $WO_3$ thin film in the o.1N $H_2SO_4$ aqueous solution, the intercalation reaction of lithium cation into $WO_3$ thin film in the 1M $LiClO_4/PC$ organic solution was shown that the stable bleaching and coloration was appeared within 1.0V of the applied overpotential. When the overpotential of electrochromic reaction for lithium cation in the 1M $LiClO_4/PC$ organic solution had been applied up to 1.5V, the accumulation phenomenon of lithium in amorphous $WO_3$ thin film layer occurred because the inserted lithium into amorphous $WO_3$ thin layer for coloring process was not fully removed from the thin layer to the electrolyte during bleaching process. It was found that there is a limitation of applied overpotential for coloring process by the reduction of the current densities of bleaching and coloration after few number of coloring and bleaching cycles.

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Characteristic of Pd-Cu-Ni Alloy Hydrogen Membrane using the Cu Reflow (Cu Reflow를 이용한 Pd-Cu-Ni 합금 수소분리막 특성)

  • Kim, Dong-Won;Kim, Heung-Gu;Um, Ki-Youn;Kim, Sang-Ho;Lee, In-Seon;Park, Jong-Su;Ryi, Shin-Kun
    • Korean Chemical Engineering Research
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    • v.44 no.2
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    • pp.160-165
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    • 2006
  • A Pd-Cu-Ni alloyed hydrogen membrane has fabricated on porous nickel support formed by nickel powder. Porous nickel support made by sintering shows a strong resistance to hydrogen embrittlement and thermal fatigue. Plasma surface modification treatment is introduced as pre-treatment process instead of conventional HCl wet activation. Nickel was electroplated to a thickness of $2{\mu}m$ in order in to fill micropores at the nickel support surface. Palladium and copper were deposited at thicknesses of $4{\mu}m$ and $0.5{\mu}m$, respectively, on the nickel coated support by DC sputtering process. Subsequently, copper reflow at $700^{\circ}C$ was performed for an hour in $H_2$ ambient. And, as a result PdCu-Ni composite membrane has a pinhole-free and extremely dense microstructure, having a good adhesion to the porous nickel support and infinite hydrogen selectivity in $H_2/N_2$ mixtures.

Pollen morphology of Patrinieae Höck (Valerianaceae) (마타리족(Patrinieae Höck, 마타리과)의 화분형태학적인 연구)

  • Jung, Eun-Hee;Hong, Suk-Pyo
    • Korean Journal of Plant Taxonomy
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    • v.38 no.2
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    • pp.163-177
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    • 2008
  • Pollen grains of 17 taxa (14 species with two additional subspecies and one variety) of genera Patrinia Juss. and Nardostachys DC. in tribe Patrinieae (Valerianaceae) were studied using light microscope, scanning electron microscope, and transmission electron microscope. Pollen grains are medium ($37.41{\times}43.60{\mu}m$ - $45.65{\times}48.50{\mu}m$) to large ($54.88{\times}59.41{\mu}m$ - $61.70{\times}71.00{\mu}m$) in size, tricolpate (rarely tetracolpate) with the characteristic halo surrounding the aperture. In equatorial view, the pollen is oblate to subprolate, and in polar view, it is mostly circular or rarely 3-lobed. Two major pollen types are recognized on the basis of exine sculpturing patterns; Type I: Exine is composed of echinae together with sparse or dense microechinae, and verrucae shallow or rarely absent (Nardostachys and sections Paleopatrinia, and Monanadropatrinia of Patirinia). - Type II: Exine is composed of massive echinae together with dense microechinae, and prominent verrucae (section Centrotrinia of Patrinia). In TEM sections, columellae are extended from the footlayer into verrucae, and exine thickness is uniform at the pole and equator. Additionally, the infrageneric classification systems of the Patrinieae were evaluated on the basis of the present data.

Enhancements of Crystallization and Opto-Electrical performance of ZnO/Ti/ZnO Thin Films (ZnO/Ti/ZnO 박막의 결정성 및 전기광학적 완성도 개선 연구)

  • Jin-Kyu Jang;Yu-Sung Kim;Yeon-Hak Lee;Jin-Young Choi;In-Sik Lee;Dae-Wook Kim;Byung-Chul Cha;Young-Min Kong;Daeil Kim
    • Journal of the Korean institute of surface engineering
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    • v.56 no.2
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    • pp.147-151
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    • 2023
  • Transparent ZnO (100 nm thick) and ZnO/Ti/ZnO (ZTZ) films were prepared with radio frequency (RF) and direct current (DC) magnetron sputtering on the glass substrate at room temperature. During the ZTZ film deposition, the thickness of the Ti interlayer was varied, such as 6, 9, 12, and 15 nm, while the thickness of ZnO films was kept at 50 nm to investigate the effect of the Ti interlayer on the crystallization and opto-electrical performance of the films. From the XRD pattern, it is concluded that the 9 nm thick Ti interlayer showed some characteristic peaks of Ti (200) and (220), and the grain size of the ZnO (002) enlarged from 13.32 to 15.28 nm as Ti interlayer thickness increased. In an opto-electrical performance observation, ZnO single-layer films show a figure of merit of 1.4×10-11 Ω-1, while ZTZ films with a 9 nm-thick Ti interlayer show a higher figure of merit of 2.0×10-5 Ω-1.

3-D Inversion of 3-D Synthetic DC Resistivity Data for Vein-type Ore Deposits (국내 맥상광체조사를 위한 3차원 전기비저항 모델링자료의 3차원 역산 해석)

  • Lee, Ho-Yong;Jung, Hyun-Key;Jeong, Woo-Don;Kwak, Na-Eun;Lee, Hyo-Sun;Min, Dong-Joo
    • Journal of the Korean earth science society
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    • v.30 no.6
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    • pp.699-708
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    • 2009
  • Recently as the interest in the development of domestic ore deposits has increased, we can easily find some studies on exploration geophysics-based ore-deposit survey in literature. Based on the fact that mineralized zone are generally more conductive than surrounding media, electrical resistivity survey among several geophysical surveys has been applied to investigate metallic ore deposits. Most of them are grounded on 2-D survey. However, 2-D inversion may lead to some misinterpretation for 3-D geological structures. In this study, we investigate the feasibility of the 3-D electrical resistivity survey to 3-D vein-type ore deposits. We first simulate 2-D dipole-dipole survey data for survey lines normal to the strike and 3-D pole-pole survey data, and then perform 3-D inversion. For 3-D ore-body structures, we assume a width-varying dyke, a wedge-shaped, and a fault model. The 3-D inversion results are compared to 2-D inversion results. By comparing 3-D inversion results for 2-D dipole-dipole survey data to 3-D inversion results for 3-D pole-pole survey data, we could note that the 2-D dipole-dipole survey data yield better inversion results than the 3-D pole-pole data, which is due to the main characteristic of the pole-pole array. From these results, we are convinced that if we have certain information on the direction of the strike, it would be desirable to apply 2-D dipole-diple survey for the survey lines normal to the strike. However, in most cases, we do not have any information on the direction of the strike, because we already developed the ore deposit with the outcrops and the remaining ore deposits are buried under the surface. In that case, performing 3-D pole-pole electrical resistivity survey would be a reasonable choice to obtain more accurate interpretation on ore body structure in spite of low resolution of pole-pole array.

MIMIC 94 GHz high isolation single balanced cascode mixer (94 GHz 대역의 높은 격리 특성의 MIMIC single balanced cascode 믹서)

  • Lee, Sang-Jin;An, Dan;Lee, Mun-Kyo;Moon, Sung-Woon;Bang, Suk-Ho;Baek, Tae-Jong;Kwon, Hyuk-Ja;Jun, Byoung-Chul;Yoon, Jin-Seob;Rhee, Jin-Koo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.9
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    • pp.25-33
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    • 2007
  • In this paper, the high isolation and wideband 94 GHz MIMIC(Millimeter-wave Monolithic Integrated Circuit) single balanced cascode mixer was designed and fabricated. Also, we designed and fabricated a 3 dB tandem coupler which has a high isolation and wideband characteristic. The single balanced resistive mixer which does not require an external IF balun was designed using the 0.1 ${\mu}m$ InGaAs/InAlAs/GaAs metamorphic HEMT(High Electron Mobility Transistor). The DC characteristics of MHEMT's are 665 mA/mm of drain current density, 691 mS/mm of maximum transconductance. The current gain cut-off frequency($f_T$) is 189 GHz and the maximum oscillation frequency($f_{max}$) is 334 GHz. A 94 GHz single balanced cascode mixer was fabricated using our 0.1 ${\mu}m$ MHEMT MIMIC process. From the measurements, the fabricated couplers showed wideband characteristics. The conversion loss of single balanced cascode mixer was 9.8 dB at an LO power of 10.9 dBm. The LO to RF isolation of single balanced cascode mixer was 29.5 dB at 94 GHz. We obtained in this study a higher LO-RF isolation compared to some other single balanced mixers.