• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.3
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• pp.219-232
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• 2013

This paper presents a microstrip antenna which recovers its resonant frequency and impedance shifted automatically by the approach of other objects such as hands. This can be used for telemetry sensor applications in the ultrahigh frequency(UHF) industrial, scientific, and medical(ISM) band. It is the key element that an frequency-reconfigurable antenna could be electrically controlled. This antenna is miniaturized by loading the folded plates at both radiating edges, and varactor diodes are installed between the radiating edges and the ground plane to control the resonant frequency by adjusting the DC bias asymmetrically. Using this voltage-controlled antenna and the micro controller peripheral circuits of reading the returned level, the antenna is designed and fabricated which recovers its resonant frequency and impedance automatically. Designed frequency auto recovering antenna is conformed to be recovered within a few seconds when the resonant frequency and impedance are shifted by the approach of other objects such as hand, metal plate, dielectric and so on.

• Korean Journal of Materials Research
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• v.5 no.6
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• pp.754-762
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• 1995

Strontium titanate(SrTiO$_3$) thin film was prepared on Si substrates by RF magnetron sputtering for a high capacitance density required for the next generation of LSTs. The optimum deposition conditions for SrTiO$_3$thin film were investigated by controlling the deposition parameters. The crystallinity of films and the interface reactions between SrTO$_3$film and Si substrate were characterized by XRD and AES respectively. High quality films were obtained by using the mixed gas of Ar and $O_2$for sputtering. The films were deposited at various bias voltages to obtain the optimum conditions for a high quality file. The best crystallinity was obtained at film thickness of 300nm with the sputtering gas of Ar+20% $O_2$and the bias voltage of 100V. The barrier layer of Pt(100nm)/Ti(50nm) was very effective in avoiding the formation of SiO$_2$layer at the interface between SrTiO$_3$film and Si substrate. The capacitor with Au/SrTiO$_3$/Pt/Ti/SiO$_2$/Si structure was prepared to measure the electric and the dielectric properties. The highest capacitance and the lowest leakage current density were obtained by annealing at $600^{\circ}C$ for 2hrs. The typical specific capacitance was 6.4fF/$\textrm{cm}^2$, the relative dielectric constant was 217, and the leakage current density was about 2.0$\times$10$^{-8}$ A/$\textrm{cm}^2$ at the SrTiO$_3$film with the thickness of 300nm.