• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.11B no.3
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• pp.112-118
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• 2001

In the near future, the voltage of power system for passenger vehicle will be changed to 42V from existing 14V./ Because of increasing power and voltage ratings used in the vehicle the motor drive system has high switching dv/dt and it generates electromagnetic interference (EMI) To solve these problems multi-level inverter system may be used The feature of multi-level inverter is the output voltage to be synthesized from several levels of voltage Because of this feature high switching dv/dt and EMI can be reduced in the multi-level inverter system But as the number of level is increased manufacturing cost is getting expensive and system size is getting large. Because of these disadvantages the application of multi-level inverter has been restricted only to high power drives. The method to reduce manufacturing cost and system size is to integrate circuit of multi-level inverter into a few chips But isolated power supply and signal isolation circuit using transformer or opto-coupler for drive circuit are obstacles to implement the integrated circuit (IC) In this paper a drive circuit of 4-level inverter suitable for integration to hybrid or one chip is proposed In the proposed drive circuit DC link voltage is used directly as the power source of each gate drive circuit NPN transistors and PNP transistors are used to isolate to transfer the control signals. So the proposed drive circuit needs no transformers and opto-couplers for electrical isolation of drive circuit and is constructed only using components to be implemented on a silicon wafer With th e proposed drive circuit 4- level inverter system will be possible to be implemented through integrated circuit technology Using the proposed drive circuit 4- level inverter system is constructed and the validity and characteristics of the proposed drive circuit are proved through the experiments.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.8
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• pp.1227-1234
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• 2013

An analog array with a 1.2 double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.30-37
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• 1998

An analog array with a 1.2 $\mu\textrm{m}$ double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• Journal of Ocean Engineering and Technology
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• v.25 no.6
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• pp.1-8
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• 2011

This paper describes a new method for a digital gas metal arc welding (GMAW) system. The GMAW system is an arc welding process that incorporates the GMAW power source (PS-GMAW) with a wire feed unit (WFU). The PS-GMAW requires an electric power of constant voltage. A constant magnitude is maintained for the arc current by controlling the wire-feed speed of the WFU. A mathematical model is derived, and a self-tuning fuzzy proportional-integral-derivative (PID) controller is designed and applied to control the welding current. The electrode wire feeding mechanism with this controller is driven by a DC motor, which can compensate for both the molten part of the electrode and undesirable fluctuations in the arc length during the welding process. By accurately maintaining the output welding current and welding voltage at constant values during the welding process, excellent welding results can be obtained. Simulation and experimental results are shown to prove the effectiveness of the proposed controller.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.7 no.2
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• pp.36-40
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• 1993

In order to improve complicated construction and complex control which are disadvantage of optimal PWM technique aimed at harmonic elimination method, this paper presented MRA(Model Reference Adaptive) PWM technique that gatmg signal of inverter is generated by comparing the reference signal with the induced feedback signal at the reference model of load. Design of controller is composed of microprocessor and analog circuit. MRA PWM technique used in the paper is able to compensate the degradation of voltage efficiency to be generated by the ratio of the output voltage to the DC supply voltage being low for using conventional sinusoidal PWM technique. When the trapezoidal signal is employed as the reference signal. the low order harmonics of line current can be reduced and the switching pattern is made by on-line computation using comparatively simple numerical analysis.

• Progress in Superconductivity
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• v.7 no.1
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• pp.46-51
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• 2005

We have developed control electronics to operate flux-locked loop (FLL), and analog signal filters to process FLL outputs for 64-channel Double Relaxation Oscillation SQUID (DROS) magnetocardiography (MCG) system. Control electronics consisting of a preamplifier, an integrator, and a feedback, is compact and low-cost due to larger swing voltage and flux-to-voltage transfer coefficients of DROS than those of dc SQUIDs. Analog signal filter (ASF) serially chained with a high-pass filter having a cut-off frequency of 0.1 Hz, an amplifier having a gain of 100, a low-pass filter of 100 Hz, and a notch filter of 60 Hz makes FLL output suitable for MCG. The noise of a preamplifier in FLL control electronics is $7\;nV/{\surd}\;Hz$ at 1 Hz, $1.5\;nV/{\surd}\;Hz$ at 100 Hz that contributes $6\;fT/{\surd}\;Hz$ at 1 Hz, $1.3\;fT/{\surd}\;Hz$ at 100 Hz in readout electronics, and the noise of ASF electronics is $150\;{\mu}V/{\surd}\;Hz$ equivalent to $0.13\;fT/{\surd}\;Hz$ within the range of $1{\sim}100\;Hz$. When DROSs are connected to readout electronics inside a magnetically shielded room, the noise of 64-channel DROS system is $10\;fT/{\surd}\;Hz$ at 1 Hz, $5\;fT/{\surd}\;Hz$ at 100 Hz on the average, low enough to measure human MCG.

• Journal of Electrical Engineering and Technology
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• v.11 no.3
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• pp.629-638
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• 2016

This paper proposes a State-of-Charge (SOC) balancing control of Battery Power Modules (BPMs) for a modularized battery for Electric Vehicles (EVs) without additional balancing circuits. The BPMs are substituted with the single converter in EVs located between the battery and the inverter. The BPM is composed of a two-phase interleaved boost converter with battery modules. The discharge current of each battery module can be controlled individually by using the BPM to achieve a balanced state as well as increased utilization of the battery capacity. Also, an SOC balancing method is proposed to reduce the equalization time, which satisfies the regulation of a constant DC-link voltage and a demand of the output power. The proposed system and the SOC balancing method are verified through simulation and experiment.

• Journal of Power Electronics
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• v.10 no.6
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• pp.777-783
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• 2010

In order to drive gas discharge lamps, DC-AC converters with a LCC resonant tank, whose output voltage is adjusted by a variable frequency control are frequently used. However, when they are activated by varying the operating frequency, converters are frequently damaged by unstable operation, due to the rising and falling of the operating frequency near the resonant frequency. To solve this problem, a simple protection circuit for the power supply of a gas discharge lamp is proposed in this paper. This circuit senses the primary current of the main transformer. Using this protection circuit, the operating frequency of the lamp driving inverter system is kept close to and on the right side of the resonant frequency and the inverter is always operated in the ZVS condition. The resulting stable variable frequency operation allows various gas discharge lamps to be tested without the risk of damaging the main switches, because the protection circuit can protect the power MOSFETs of bridge converters from abnormal conditions. The validity and effectiveness of the proposed protection circuit are verified through the experimental results.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.9
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• pp.5440-5445
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• 2014

Many studies have examined robot control using human bio signals but complicated signal processing and expensive hardware are necessary. This study proposes a method to recognize a human's hand motion using a low-cost EMG sensor and Flex sensor. The method to classify movement of the hand and finger is determined from the change in output voltage measured through MCU. The analog reference voltage is determined to be 3.3V to increase the resolution of movement identification through experiment. The robotic hand is designed to realize the identified movement. The hand has four fingers and a wrist that are controlled using pneumatic cylinders and a DC servo motor, respectively. The results show that the proposed simple method can realize human hand motion in a remote environment using the fabricated robotic hand.

• ETRI Journal
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• v.36 no.3
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• pp.352-360
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• 2014

This paper presents a 900 MHz zero-IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ${\Delta}{\Sigma}$ fractional-N frequency synthesizer. In the RF front end, re-use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current-driven passive mixer in Rx and voltage-mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty-cycle in local oscillator clocks. The overall Rx-baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a $0.18{\mu}$ CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of -2 dBm, a sensitivity level of -103 dBm at 100 Kbps with PER < 1%, an Rx input $P_{1dB}$ of -11 dBm, and an Rx input IP3 of -2.3 dBm.