• The Transactions of the Korean Institute of Electrical Engineers P
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• v.65 no.1
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• pp.18-24
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• 2016

In order to service restoration and enhance power system reliability, a number of impedance based fault location algorithms have been developed for fault locating in a transmission line. This paper presents an advanced impedance-based fault location algorithms in a two-ended sources transmission line to reduce the DC offset error effects. This fault location algorithm uses of the GPS time synchronized voltage and current signals from the local and remote terminal. The algorithm uses an advanced DC offset removal filter. A series of test results using ATPdraw simulation data show the performance effectiveness of the proposed algorithm. The proposed algorithm is valid for a two-end sources transmission network.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.3
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• pp.685-690
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• 2013

This paper has proposed a multi-channel and wide gain-range baseband circuit blocks for the IEEE 802.15.4g MR-OFDM SUN systems. The proposed baseband circuit blocks consist of two negative-feedback VGAs, an active-RC 5th-order chebyshev low-pass-filter, and a DC-offset cancellation circuit. The proposed baseband circuit blocks provide 1 dB cut-off frequencies of 100 kHz, 200 kHz, 400 kHz, and 600 kHz respectively, and achieve a wide gain-range of +7 dB~+84 dB with 1 dB step. In addition, a DC-offset cancellation circuit has been adopted to mitigate DC-offset problems in direct-conversion receiver. Simulation results show a maximum input differential voltage of $1.5V_{pp}$ and noise figure of 42 dB and 37.6 dB at 5 kHz and 500 kHz, respectively. The proposed I-and Q-path baseband circuits have been implemented in $0.18-{\mu}m$ CMOS technology and consume 17 mW from a 1.8 V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.2 s.93
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• pp.144-148
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• 2005

In this paper, we have proposed VGA fur MB-OFDM UWB application using $CMOS\;0.18\;{\mu}m$ technique. The proposed VGA can vary power gain from 45 dB to -6 dB and 3 dB band width is more than 264 MHz. It has 3-stage cascade structure and DC offset cancellation. It consumes less, than 4 mA for 1.8 V bias voltage.

• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.104-106
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• 2018

The harmonics and the DC offset in the grid can cause serious synchronization problems for grid connected inverters (GCIs) which leads not able to satisfy the IEEE 519 and p1547 standards in terms of phase and frequency variations. In order to guarantee the smooth and reliable synchronization of GCIs with the grid, Phase Locked Loop (PLL) is the crucial element. Typically, the performance of the PLL is assessed to limit the grid disturbances e.g. grid harmonics, DC Offset and voltage sag etc. To ensure the quality of GCI, the PLL should be precise in estimating the grid amplitude, frequency and phase. Therefore, in this paper a novel Robust PLL technique called Digital Lock-in Amplifier (DLA) PLL is proposed. The proposed PLL estimate the frequency variations and phase errors accurately even in the highly distorted grid voltage conditions like grid voltage harmonics, DC offsets and grid voltage sag. To verify the performance of proposed method, it is compared with other six conventional used PLLs (CCF PLL, SOGI PLL, SOGI LPF PLL, APF PLL, dqDSC PLL, MAF PLL). The comparison is done by simulations on MATLAB Simulink. Finally, the experimental results are verified with Single Phase GCI Prototype.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2006.07a
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• pp.419-419
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• 2006

• Proceedings of the KOSOMBE Conference
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• v.1997 no.11
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• pp.287-290
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• 1997

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2001.11a
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• pp.222-226
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• 2001

In this paper, 2.4GHz RF Module using Even Harmonic Mixer(EHM) was designed and fabricated for Direct conversion(DC) system. By minimizing performance degradation of DC system with DC offset and LO radiation, the capability of minimization and one chip solution in wireless system was proposed. The designed EHM using anti-parallel diode pair represented 9dB conversion loss and about -60dBm 2LO leakage radiation in RF port, and output reflection and reverse transmission characteristic of low noise amplifier was improved. So superior DC offset suppression characteristic is expected. RF Module which consists of EHM, LNA, RF amplifier, Frequency synthesizer and Duplexer was designed and fabricated.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.469-471
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• 2022

This paper presents an implementation of a calibration circuit to correct the gain error, DC offset and sampling clock phase error generated in the process of converting digital pixels to analog pixels to drive an analog-driven 4K UHD LCOS panel. The proposed calibration circuit consists of a gain and DC offset adjustment circuit and a sampling clock phase adjustment circuit. The calibration circuit is implemented with an FPGA device, and video amplifiers.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.8
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• pp.1360-1365
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• 2010

In this paper, we propose a distance relaying algorithm using a Discrete Fourier Transform (DFT)-based modified phasor estimation method to eliminate the adverse influence of exponentially decaying DC offsets. Most distance relays are based on estimating phasors of the voltage and current signals. A DFT is generally used to calculate the phasor of the fundamental frequency component in digital protective relays. However, the output of the DFT contains an error due to exponentially decaying DC offsets. For this reason, distance relays have a tendency to over-reach or under-reach in the presence of DC offset components in a fault current. Therefore, the decaying DC components should be taken into consideration when calculating the phasor of the fundamental frequency component of a relaying signal. The error due to DC offsets in a DFT is calculated and eliminated using the outputs of an even-sample-set DFT and an odd-sample-set DFT, so that the phasor of the fundamental component can be accurately estimated. The performance of the proposed algorithm is evaluated for a-phase to ground faults on a 345 kV, 50 km, simple overhead transmission line. The Electromagnetic Transient Program (EMTP) is used to generate fault signals. The evaluation results indicate that adopting the proposed algorithm in distance relays can effectively suppress the adverse influence of DC offsets.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.1
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• pp.1-8
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• 2011

The accuracy of MR sensor-based electronic compass is influenced by the temperature drift and DC offset of the MR sensor and the OP-amp, the magnetic distortion of nearby magnetic materials, and the compass tilt We design the 3-axis MR sensor and accelerometers-based electronic compass which is compensated by the set/reset pulse switching method on the temperature drift and DC offset, by the execution of hard-iron calibration routine on the magnetic distortion, and by the execution of the Euler rotational equation on the compass tilt. We qualitatively analyze the measured azimuth error on the execution of sensitivity calibration routine which is the normalization process on the different sensitivity of each MR sensor and the different gain of each op-amps. This compensation and analytic result make us design the one degree accuracy electronic compass.