• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.813-816
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• 2005

This paper presents a method for harmonic elimination and reactive power compensation using an intervening firing method and passive power filter with is suitable to compensate rapidly changing loads and reactive power. The proliferation of three-phase thyristor phase-controlled converter of DC motor drives into a power system has the potential to increase the harmonic levels in the power system. The design procedure of an intervening firing method and passive power filter capable of reducing the voltage and current harmonics produced by converter supplied from a source having internal large inductive impedance is offered. The analysis uses the or CAD PSpice to model three-phase thyristor phase-controlled converter of DC motor drives as well as the system.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.789-792
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• 2003

본 논문은 고전력 응용에 적합한 3상 멀티레벨 AC/DC컨버터의 THD를 분석하였다 회로는 일반 적인 NPC (Neutral Point Clamped)컨버터 타입을 채택하였고, 3레벨과 5레벨의 레벨수 증가에 따른 고조파를 분석하여 THD를 해석하였다. 공간벡터 PWM은 레벨이 증가할수록 벡터 공간도 증가하므로 영역판별이 어렵다는 단점이 있어 멀티 캐리어 PWM 방법을 사용하여 시스템을 분석하였다.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.156-157
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• 2010

This paper proposes a correction method of capacitance estimation considering the temperature effect for the DC-link capacitor banks in three-phase AC/DC PWM converters. In this work, a sensing circuit using a temperature sensor is designed for measuring the operating temperature. Capacitance value is corrected considering the measured temperature. This method has been implemented in experiment.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.109-112
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• 1988

All parasitics such as switch conduction voltages, conduction resistances, switching times and ESR''s of capacitors are counted in the new state-space modeling based on non-ideal switching functions. An equivalent simplified model is derived from the complex circuit with parasitics. Hence the results are very simple and exact, which are very important features of modelings. The pole frequency, dc voltage gain, and efficiency of the general converter, the buck-boost converter are analyzed and verified by the experiments with good agreements with the theories. This may be a good summary for the previous works concerned with parasitics.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.31-33
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• 2008

A novel lossless current sensing technique for a synchronous buck converter is presented. The inductor DCR method is generally used as a low cost and lossless current sensing technique of DC/DC converters. It is however difficult to obtain the accurate current value for the conventional DCR method because the inductor resistance varies depending on the operating frequency. In order to overcome this problem, an improved current sensing technique is proposed, which has the separated DC and AC sensing circuits. The concept and operation of the proposed method are explained and the experimental results are provided to show its effectiveness.

• Journal of international Conference on Electrical Machines and Systems
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• v.1 no.3
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• pp.360-365
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• 2012

Cascaded H-Bridge rectifier (CHBR) is a more attractive solution in traction application for its transformerless structure. Because of the currents of different cells are exactly the same one, it is a challenge job to regulate the voltages of cells with only one current controller. In this paper, a PI-based control scheme is presented to deal with the voltages balance issue in CHBR. To satisfy the demand of rectifier such as unity power factor and regulated output DC voltages, the proposed control scheme consists of two parts. One is for shaping the grid current waveform and regulating the sum of DC-link voltages of all the cells; the other one is for balancing DC-link voltages. The latter is more concerned in this paper and is discussed in detail especially. Simulations and experiments are carried on. The results verified the feasibility and effectiveness of the proposed scheme.

• Journal of Power Electronics
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• v.13 no.1
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• pp.113-121
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• 2013

This paper introduces a simple core loss calculation method for output filter inductor in pulse width modulation (PWM) DC-AC inverter. Amorphous C-core (AMCC-320) is used to analyze the core loss. In order to measure core loss of the output filter inductor and validate the proposed method, a single-phase half-bridge inverter and a calorimeter are used. By changing switching frequency and modulation index (MI) of the inverter, core loss of the AMCC-320 is measured with the lab-made calorimeter and the results are compared with calculated core loss. The proposed method can be easily extended to other core loss calculation of various converters.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1336-1338
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• 2000

This paper proposed the single phase multi-level PWM AC/DC converter using binary combine which controls input current by combining buck converters to improve input current characteristic, and confirmed its validity throughout simulation and experiment. This method, which is multiplying and duplicating output of converter of equal capacity, has the advantage of being able to control unit power factor of input current and reducing of the problem caused by high frequency switching, and appling to high power converter because filter is not necessary etc.

• KIEE International Transactions on Power Engineering
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• v.4A no.4
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• pp.178-191
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• 2004

This paper presents a new approach to HVDC system control for damping subsynchronous oscillation (SSO) involving HVDC converters and turbine generator shaft systems. This requires a novel eigenvalue analysis (NEA) program, derivation of HVDC system modeling considering steady-state conditions and dynamic conditions in the combined AC/DC system, and an appropriate control scheme. The method suggested makes possible the design of a subsynchronous oscillation damping controller (SODC) to provide positive damping torque for the range of torsional modes in combined AC/DC systems. There are three steps involved in the design of a SODC； first the worst torsional mode is determined using the NEA program, next the SODC parameters are designed for the range of that torsional mode, and then finally an off-line simultaneous time domain program such as PSCAD/EMTDC is used to verify the parameters of the SODC. The suggested SODC design method is applied to two AC/DC systems, and its practicality is verified using the PSCAD/EMTDC simulation program.

• Journal of Power Electronics
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• v.14 no.4
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• pp.796-805
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• 2014

A digital controller with a low-power approach for point-of-load synchronous buck converters is discussed and compared with its analog counterpart to confirm its feasibility for system integration. The tri-mode digital controller IC in $0.35{\mu}m$ CMOS process is presented to demonstrate solutions that include a PID, quarter PID, and robust RST compensators. These compensators address the steady-state, stand-by, and transient modes according to the system operating point. An idle-tone free condition for ${\Sigma}-{\Delta}$ DPWM reduces the inherent tone noise under DC-excitation. Compared with that of the traditional approach, this condition generates a quasi-pure modulation signal. Experimental results verify the closed-loop performances and confirm the power-saving mechanism of the proposed controller.