• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.7
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• pp.1285-1289
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• 2008

In this paper, we design COMS system bus that the 1553 Data Bus is able to link all the units of the satellite managed by the SCU using one Prime Data Bus and on Redundant Data Bus. Also we analyze MIL-STD-1553B bus load and relevant exchange memory budgets in system bus of the COMS satellite. This data is used in the satellite mission and software design by system engineer.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.4 no.3 s.8
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• pp.51-59
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• 2005

To improve the quality of bus service, providing bus ravel time information to passenger through station screen. Generally, bus travel time information predict by using previous bus data such as neural network, Kalman filtering, and moving average algorithms. However, when they got a difficulty about bus travel time information because of the missing previous bus data, they use pattern data. Generally, nevertheless the difference of range is big. Hence in this research to calculate the bus travel time information when the bus information is missed, use queue detector's data which set up in link. The application of several factors which influence in bus link travel time, we used CORSIM Version 5.1 simulation package.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.117-126
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• 2012

This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively

• Journal of the Korean Society for Aviation and Aeronautics
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• v.17 no.3
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• pp.70-77
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• 2009

We proposed the method of avionics integrated architecture using high-speed fiber optic bus. Typically, data bus of aircraft consists of electronic and optic data transmission method. Avionics systems are difficult to operate the electronic data transmission method for the high speed data processing, synchronization and interconnection between flight control system and flight management system efficiently. In this paper, it is known to look into the problem of data bus and the advanced trend in avionics systems, and propose the appropriate data bus of the advanced avionics systems.

• Journal of Auto-vehicle Safety Association
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• v.12 no.4
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• pp.39-47
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• 2020

In this study, crash situations of representative bus crash types were elicited by analyzing a total of 1,416 bus repair record which were collected in 2018~2019. K-means clustering was used as a methodology for this study. Bus repair record contain the information of repair term, type of bus operation, responsibility of accident, weather condition, road surface condition, type of accident, other party, type of road and type of location for each data. Also, by checking collision parts of each bus repair record, each record was classified by types of collision regions. From this, 760 record are classified to frontal type, 363 record are classified to middle-frontal type, 374 record are classified to middle-rear type and 331 record are classified to rear type. As mentioned, k-means clustering was performed on each type of collision parts. As a result, this study analyzed the severity of bus crash based on actual bus accident data which are based on bus repair record not the crash data from the TAAS. Also, this study presented crash situation of representative bus crash types. It is expected that this study can be expanded to analyzing hydrogen bus crash and defining indicators of hydrogen bus safety.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.6
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• pp.1045-1054
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• 2006

In this paper, described a design result of bus interface modulo for multiple level MU-SID-1553 data bus network. In general, MIL-SID-1553 network is used for single level data bus topology. But, according to applied system's structure. multiple level bus architecture is required., And for his, micro processor must be involved for system be, and a additional hardware and software functions are needed. The designed data bus interface module is simply consists of communication transceivers and simple electronic circuit without micro processor. Through the hardware testing and software simulation, the functional performance of the designed interface module was successfully validated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.96-102
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• 2008

The SoC bus topology is classified to single and multiple bus systems due to bus number. In single bus system, the selected only one master among the masters that try to initiate the bus transaction can execute its data transaction. On the other hand, in multiple bus system, as several buses that can be operated independently are connected with bridge, multiple data can be transferred parallel in each bus. However, In the case of data communication from one bus system to the other, data latency has remarkably increased in multiple bus. Furthermore, the performance of multiple bus can be easily different from master number, slave type and so on. In this paper, the performance of single and multiple bus architecture is compared and quantitatively analysed with the variation of master number and slave type especially a tying SDRAM, SRAM and register with TLM simulation method.

• Journal of KIBIM
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• v.8 no.3
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• pp.12-19
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• 2018

The research aims to find implications of machine learning and urban big data as a way to construct the flexible transportation network system of smart city by responding the urban context changes. This research deals with a problem that existing a bus headway model is difficult to respond urban situations in real-time. Therefore, utilizing the urban big data and machine learning prototyping tool in weathers, traffics, and bus statues, this research presents a flexible headway model to predict bus delay and analyze the result. The prototyping model is composed by real-time data of buses. The data is gathered through public data portals and real time Application Program Interface (API) by the government. These data are fundamental resources to organize interval pattern models of bus operations as traffic environment factors (road speeds, station conditions, weathers, and bus information of operating in real-time). The prototyping model is implemented by the machine learning tool (RapidMiner Studio) and conducted several tests for bus delays prediction according to specific circumstances. As a result, possibilities of transportation system are discussed for promoting the urban efficiency and the citizens' convenience by responding to urban conditions.

• Journal of IKEEE
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• v.13 no.2
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• pp.101-107
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• 2009

Growth in the VLSI process and design technology is resulting into a continuous increase in the number of IPs on a chip to form a system. Because of many IPs on a single chip, efficient communication between IPs is essential. We propose a dynamically reconfigurable 3-layer bus structure which can adapt to the pattern of data transmission to achieve an efficient data communication between various IPs. The proposed 3-layer bus can be reconfigured to multi-single bus mode, and single-multi bus mode, thus providing the benefits of both single-bus and multi-bus modes. Experimental results show that the flexibility of the proposed bus structure can reduce data transmission time compared to the conventional fixed bus structure. We incorporated the proposed bus structure in a JPEG system and verified that the proposed structure achieved an average of 22% improvement in time over the conventional fixed bus structure.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.34-41
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• 1998

In this paper, I designed a P1394 serial bus chip as new bus interface architecture which can transmit the multimedia data at the rate of 400 Mbps and guarantee necessary bandwidth. because multimedia data become meaningless data after appropriate time, it is necessary to transfer multimedia data in real time, P1394 serial bus chip designed in this paper support isochronous transfer mode to solve this problem. Also, designed P1394 serial bus chip can transfer high quality video data or high quality audio data because it support the speed of 400 Mbps. While user must set device ID manually in previous interface such as SCSI, device ID is automatically determined if user connect each node with designed P1394 serial bus cable and power on. To design this chip, I verified the behavioral of the entrire system and synthesized layout. Also, I did layout the analog blocks and blocks which must be optimized in full custom.