• International Journal of Industrial Entomology and Biomaterials
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• v.6 no.2
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• pp.179-181
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• 2003

$F(ab`)_2$-ELISA and direct antigen coating-ELISA (DAC-ELISA) were evaluated in the detection of purified Bombyx mori nuclear polyhedrosis virus (BmNPV) and nuclear polyhedrosis virus infection in silkworm larvae inoculated with BmNPV polyhedra. Although nanogram levels of BmNPV was detected in both DAC- and $F(ab`)_2$-ELISA, similar concentrations of antigen was detected in case of F(ab’)$_2$-ELISA even at higher dilution of antibody (up to 1 : 20 K). One hundred percent nuclear polyhedrosis infection was detected 6 hrs after inoculation in BmNPV infected silkworm larvae by $F(ab`)_2$-ELISA. On the other hand, detection of 100% infection was observed only three days after inoculation in DAC-ELISA. In this study, it was observed $F(ab`)_2$-ELISA was more sensitive than DAC-ELISA in the detection of purified BmNPV as well as nuclear polyhedrosis infection in silkworm larvae.

• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.115-120
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• 2002

This paper presents the implementation of IS-95 CDMA signal processor, baseband and Intermediate Frequency(IF) digital converter using Field Programmable Gate Array(FPGA) and ADC/DAC and frequency up/down converter IS-95 CDMA channel processor is generated the pilot channel signal with short PN code and Walsh-code generator. The digital If is composed of FPGA. digital transmit/receive signal processor and high speed analog-to-digital converter(ADC) and digital-to-analog converter(DAC). The frequency up/down converter consisted of filter, mixer, digital attenuator and PLL is analog conversion between intermediate frequency(IF) and baseband. This implemented system can be deployed in the IS-95 CDMA base station device etc.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.257-262
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• 2000

Recently, though there are many REES(Remote Education Estimation Systems), they have some tied and complete testing method not considering for the student individual specification and characteristic. This paper proposes the education model of the distributed asynchronous communication method which making a test without me and place limits using web estimation system from problem bank database, and attach effective method could improve student achievement, quality of estimation later problem filtering using user profile in order to consider the student individual difference and characteristic that not considered pre-Remote Education Estimation Systems. This is a adaptive DAC method improving the pre-DAC method.

• Journal of Information Processing Systems
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• v.15 no.3
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• pp.670-681
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• 2019

Orthogonal frequency division multiplexing (OFDM) is a system which is used to encode data using multiple carriers instead of the traditional single carrier system. This method improves the spectral efficiency (optimum use of bandwidth). It also lessens the effect of fading and intersymbol interference (ISI). In 1995, digital audio broadcast (DAB) adopted OFDM as the first standard using OFDM. Later in 1997, it was adopted for digital video broadcast (DVB). Currently, it has been adopted for WiMAX and LTE standards. In this project, a Verilog design is employed to implement an OFDM transmitter (DAC block) and receiver (FFT and ADC block). Generally, OFDM uses FFT and IFFT for modulation and demodulation. In this paper, 16-point FFT decimation-in-frequency (DIF) with the radix-2 algorithm and direct summation method have been analyzed. ADC and DAC in OFDM are used for conversion of the signal from analog to digital or vice-versa has also been analyzed. All the designs are simulated using Verilog on ModelSim simulator. The result generated from the FFT block after Verilog simulation has also been verified with MATLAB.

• Journal of rehabilitation welfare engineering & assistive technology
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• v.7 no.2
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• pp.13-18
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• 2013

In this paper design a 8 bit Current Steering D/A Converter for stimulating neuron signal. Proposed circuit in paper shows the conversion rate of 10KS/s and the power supply of 3.3V with 0.35um Magna chip CMOS process using full custom layout design. It employes segmented structure which consists of 3bit thermometer decoders and 5bit binary decoder for decreasing glitch noise and increasing resolution. So glitch energy is down by $10nV{\bullet}sec$ rather than binary weighted type DAC. And it makes use of low power current stimulator because of low LSB current. And it can make biphasic signal by connecting with Micro Controller Unit which controls period and amplitude of signal. As result of measurement INL is +0.56/-0.38 LSB and DNL is +0.3/-0.4 LSB. It shows great linearity. Power dissipation is 6mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.7C
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• pp.713-724
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• 2006

The purpose of this study is to design, implement and verify the pre-modulation filter with the variable -3dB cutoff frequency and linear phase response for bandlimiting the allocation of radio frequency bandwidth for PCM/FM transmission. For the design of this required filter, the digital FIR filter, DAC system and tuneable 2nd order LPF have been constructed and simulated according to the attenuation characteristic requirement of the amplitude frequency response by each stage. From these results, we have implemented the filter and verified the analog conversion hardware part which is composed of DAC system and tuneable 2nd order LPF for the interpolation of the discrete sequences. Especially this paper proposes and carries out the verification processes using the tone generator and the calibration procedures for more precise frequency response of the filter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.225-228
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• 2012

In this paper, a 10-bit digital-to-analog converter (DAC) with small area is proposed. The 10-bit DAC consists of a 8-bit decoder, a 2-bit time-interpolator, and a buffer amplifier. The proposed time-interpolation is achieved by controlling the charging time through a low-pass filter composed of a resistor and a capacitor. To implement the accurate time-interpolator, a control pulse generator using a replica circuit is proposed to minimize the effect of the process variation. The proposed 10-bit Time-Interpolation DAC occupies 61 % of the conventional 10-bit resistor-string DAC. The proposed DAC is designed using a $0.35{\mu}m$ CMOS process with a 3.3 V supply. The simulated DNL and INL are +0.15/-0.21 LSB and +0.15/-0.16 LSB, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.67-74
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• 2013

A low-power 12-bit resistor string DAC for wireless sensor applications is presented. Two-step approach reduces complexity, minimizes power consumption and area, and increases speed. This chip is fabricated in 0.18-${\mu}m$ CMOS and the die area is $0.76mm{\times}0.56mm$. The measured power consumption is 1.8mW from the supply voltage of 1.8V. Measured SFDR(Spurious-Free Dynamic Range) is 70dB when the sampling frequency is less than 1 MHz.

• Journal of the Korean Society of Marine Environment & Safety
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• v.20 no.2
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• pp.210-217
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• 2014

In this paper, the volume of ODA of Korea to developing countries has been analysed quantitatively based on statistical information, compared with Korea's ODA in the scope of the maritime industry. Thereafter, norms and policies of ODA in OECD DAC and trends of ODA in international societies have been examined through literature and qualitative researches so that possible ways to forward in Korea's ODA have been proposed. Hence, in this paper it h as been recognized that the volume of ODA related with the Korean maritime industry has been standing still as the before despite tremendous increase of total volume of Korea's ODA. for last 10 years. Consequently, the paper would like to propose possible measures that might been taken by the Korean government to raise the volume of ODA related with the maritime industry.

• Applied Chemistry for Engineering
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• v.35 no.2
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• pp.85-95
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• 2024

Direct air capture (DAC) technology plays a crucial role in mitigating climate change. Reports from the International Energy Agency and climate change emphasize its significance, aiming to limit global warming to 1.5 ℃ despite continuous carbon emissions. Despite initial costs, DAC technology demonstrates potential for cost reductions through research and development, operational learning, and economies of scale. Recent advancements in high-permeance polymer membranes indicate the potential of membrane-based DAC technology. However, effective separation of CO₂ from ambient air requires membranes with high selectivity and permeability to CO₂. Current research is focusing on membrane optimization to enhance CO₂ capture efficiency. This study underscores the importance of direct air capture, evolving cost trends, and the pivotal role of membrane development in climate change mitigation efforts. Additionally, this research delved into the theoretical background, conditions, composition, advantages, and disadvantages of permeance and selectivity in membrane-based DAC.