• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.229-232
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• 2000

Orthogonal frequency division multiplexing(OFDM) has meanwhile become part of several telecommunicati ons standards, such as satellite and terrestrial digital audio broadcasting(DAB), digital terrestrial TV broad casting(DVB), asymmetric digital subscriber line(ADSL) for high-bit-rate digital subscriber services on twisted-pair channels, and broadband indoor wireless systems. In his paper, we show that OFDM signals contain sufficient structure to accomplish blind channel estimation using second order statistics only. This method doesn't require redundancy as cp in transmitter. And the result is compared with PSAM channel estimation as least square, linear minimum mean square, singular value decomposition.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1777-1780
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• 2005

OFDM(Orthogonal Frequency Division Multiplexing)은 제 4 세대 기술로 일컬어지는 변조 방식으로 최근 유럽의 디지털 오디오 방송(DAB)과 디지털 비디오 방송(DVB)에 표준으로 사용되고 있으며, IEEE 802.11a 무선 LAN 및 디지털 가입자라인 xDSL 에서도 사용되고 있다. 본 논문에서는 OFDM 모뎀 구현의 핵심이라고 할 수 있는 64-포인트 FFT(Fast Fourier Transform) 프로세서의 여러 가지 구조를 분석하고, 이들과 비교하여 성능 대 면적 비를 획기적으로 향상시킨 새로운 FFT 프로세서인 Radix-4,2 SIC (Single Instruction Computer) 구조를 제안하였다. 본 논문에서 제안하는 SIC 구조는 버터플라이 연산의 재사용을 극대화하였으며 Radix-4,2 알고리즘을 사용함으로써 FFT 프로세서에서 면적의 80%를 차지하는 복소곱셈기의 수를 감소시켜 크기를 획기적으로 줄인 결과를 보여 준다.

• Journal of Broadcast Engineering
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• v.13 no.2
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• pp.172-178
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• 2008

Orthogonal Frequency Division Multiplexing (OFDM) is one of the most promising technologies for high data rate wireless communications. OFDM has been adopted in wireless standards such as digital audio/video broadcasting. The combination of OFDM and cooperative diversity techniques can provide the diversity gain and/or increased capacity. In this paper, the cooperative coding using cyclic delay diversity (CDD) for multiuser OFDM systems is introduced. To improve the beneficial effects of relays's cooperation, CDD is adopted in cooperative transmission of relays. Simulation results show the bit error rate (BER) for various consideration. The proposed scheme provides improved performance compared to delay.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1365-1368
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• 2002

OFDM은 제4세대 변조기술로 일컬어지는 방식이다. 이는 최근 유럽에서 디지털 오디오 방송(DAB)과 디지털 비디오 방송(DVB)에 표준이 되었으며, IEEE 802.11a 무선 LAN 에서도 이 방식을 채택했고, ADSL, VDSL 등에서도 사용되어지고 있다. 본 논문에서는 이러한 OFDM 방식의 핵심이라고 할 수 있는 64포인트 FFT(Fast Fourier Transform)하드웨어 프로세서의 여러 가지의 구현된 예를 비교 분석하고, 가장 효율적인 방법인 Radix-2 SDF(Singlepath Delay Feedback)[1] 방법을 개선하여 새로운 구조를 제안하였다. 동일한 속도 성능을 가지는 여러구조 중에서 적은 수의 지연소자를 활용하여 FFT 크기를 작게 한 것이 SDF 방식으로 가장 널리 사용되고 있다. 본 논문에서는 SDF 방식이 내부적으로 4개의 복소곱셈기를 필요로 하는데 비해 2개의 복소곱셈기만을 사용하는 구조로 변형하고 컨트롤을 조절하여 새로운 구조를 설계하였다. 구현한 결과, FFT에서 전체 구조의 약 80%를 차지하는 복소곱셈기의 수를 절반으로 줄여 FFT 하드웨어 크기를 SDF 방식의 60% 정도로 줄일 수 있게 되었고, 이러한 구현방식은 64포인트 FFT만이 아닌 더 큰 크기의 FFT를 구현함에 있어서도 동일하게 적용할 수 있으며 현재 국내외에 발표된 논문 중 성능 대 면적비가 가장 우수한 구조이다.

• Journal of Information Processing Systems
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• v.15 no.3
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• pp.670-681
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• 2019

Orthogonal frequency division multiplexing (OFDM) is a system which is used to encode data using multiple carriers instead of the traditional single carrier system. This method improves the spectral efficiency (optimum use of bandwidth). It also lessens the effect of fading and intersymbol interference (ISI). In 1995, digital audio broadcast (DAB) adopted OFDM as the first standard using OFDM. Later in 1997, it was adopted for digital video broadcast (DVB). Currently, it has been adopted for WiMAX and LTE standards. In this project, a Verilog design is employed to implement an OFDM transmitter (DAC block) and receiver (FFT and ADC block). Generally, OFDM uses FFT and IFFT for modulation and demodulation. In this paper, 16-point FFT decimation-in-frequency (DIF) with the radix-2 algorithm and direct summation method have been analyzed. ADC and DAC in OFDM are used for conversion of the signal from analog to digital or vice-versa has also been analyzed. All the designs are simulated using Verilog on ModelSim simulator. The result generated from the FFT block after Verilog simulation has also been verified with MATLAB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.12 s.91
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• pp.1152-1160
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• 2004

OFDM technique was adopted as the standard of IEEE 802.1 la and it has been widely used for wireless LAN, European DVB/DAB system, Korean DMB system. In the standard of IEEE 802.11a the data packet is composed of two parts, preamble and data. Preamble is composed of short pilots and long pilots, which are used for synchronization and estimation of frequency offset and channel. We can also compensate phase noise effect in the transceiver by using above pilots. The phase noise is more complicate than frequency offset and seriously affects system performance. In this paper, we newly propose CPE and ICI simultaneous compensation method to compensate phase noise generated by transceiver oscillator and compare with previous studies. As results, phase noise effect can be significantly compensated by CPE cancellation method, PNS algorithm and our proposed CPE and ICI compensation method. Especially, the proposed CPE and ICI compensation method can achieve the best BER performance compared with original OFDM, CPE cancellation method and PNS algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.