• KSII Transactions on Internet and Information Systems (TIIS)
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• 제7권10호
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• pp.2411-2429
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• 2013

In this paper, we extend the case of information exchange error mitigation for the distributed orthogonal space-time block code (DOSTBC) for two transmit antennas to distributed quasi-orthogonal space-time block code (DQOSTBC) for four transmit antennas. A rate 1 full-diversity DQOSTBC for four transmit antennas is designed. The code matrix changes according to different information exchange error cases, so full diversity is maintained even if not all information exchange is correct. We also perform analysis of the pairwise error probability. The performance analysis indicates that the proposed rate 1 DQOSTBC outperforms rate 1/2 DOSTBC for four transmit antennas at the same transmission rate, which is confirmed by the simulation results.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(4)
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• pp.13-16
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• 2001

In the Dedicated Short Range Communication (DSRC) system channel, a large number of bit errors occur because of Additive White Gaussian Noise (AWGN) and fading. When an image data is transmitted under the condition, reconstructed image quality is significantly degraded. In this paper, as an alternative to the error correcting code and/or automatic repeat request scheme, we propose an error recovery scheme for image data transmission. We first analyze how transmission errors in the DSRC system channel degrade image quality. Then, in order to improve image quality, we propose error resilient and concealment schemes for still image transmission using DCT-based fixed length coding, hamming code, cyclic redundancy check, and interleaver. Finally, we show its performance by an experiment.

• Journal of Advanced Marine Engineering and Technology
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• 제25권2호
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• pp.375-382
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• 2001

In this study, an adapted Turbo Coding Algorithm for reducing communication error of a fire detection system for marine vessels, especially image transmission via power lone. Because it is necessary that this system communicate larger and faster than previous method, this study carried out enhancement a decoding speed by adaptation CRC with Turbo Code Algorithm, improvement of metric method, and reduction of decoding delay by using of Center-to-Top method. And the results are as follows: (1) Confirmed that a Turbo Code is so useful methods for reducing communication error in lots of noise environments. (2)Proposed technology in this study speed increasing method of Turbo Coding Algorithm proves 2 times faster than normal Turbo Code and communication error reducing as well in the board made by VHDL software & chips ALTERA company.

• 한국통신학회논문지
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• 제32권3C호
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• pp.195-204
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• 2007

The cyclic redundancy check(CRC) code used to decide retransmission request in hybrid automatic repeat request(HRAQ) system can also be used to stop iterative decoding of turbo code if it is used as an error correcting code(ECC) of HARQ system. Thus a scheme to use CRC code for both iteration stop and repeat request in the HARQ system with turbo code based on the standard of cdma 2000 system is proposed in this paper. At first, the optimum CRC code which has the minimum length without performance degradation due to undetected errors is found. And the most appropriate turbo encoder structure is also suggested. As results, it is shown that at least 32-bit CRC code should be used and a turbo code with 3 constituent encoders is considered to be the most appropriate one.

• 한국군사과학기술학회지
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• 제18권6호
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• pp.755-761
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• 2015

Satellite Air-defence Warning System receives the aircraft/ballistic track information and air defense control command obtained from Master Control & Reporting Center (MCRC) and Air Missile Defence Cell (AMD Cell) Systems. It consists of terminal and control system to propagate track information and air defense control command control via the military satellite communications. In this paper, there were described track information, air defense control command, the frame structure of modem to transmit a voice information and modulation/demodulator design, network synchronization methods via the satellite network.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제14권7호
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• pp.3156-3167
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• 2020

One drawback of polar codes is that they are not universal, that is, to achieve optimal performance, different polar codes are required for different kinds of channel. This paper proposes a polar code construction scheme for Nakagami-m fading channel. The scheme fully considers the characteristics of Nakagami-m fading channel, and uses the optimized Bhattacharyya parameter bounds. The constructed code is applied to an orthogonal frequency division multiplexing (OFDM) system over Nakagami-m fading channel to prove the performance of polar code. Simulation result shows the proposed codes can get excellent bit error rate (BER) performance with successive cancellation list (SCL) decoding. For example, the designed polar code with cyclic redundancy check (CRC) aided SCL (L = 8) decoding achieves 1.1dB of gain over LDPC at average BER about 10^-5 under 4-quadrature amplitude modulation (4QAM) while the code length is 1024, rate is 0.5.

• 한국철도학회논문집
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• 제8권1호
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• pp.1-5
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• 2005

This paper has presented the parallel cyclic redundancy check (CRC) technique that performs CRC computation in parallel superior to the conventional CRC technique that processes data bits serially. Also, it has showed that the implemented parallel CRC circuit has been successfully applied to the inductively coupled passive RFTD system working at a frequency of 13.56㎒ in order to process the detection of logical faults more fast and the system has been verified experimentally. In comparison with previous works, the proposed RFID system using the parallel CRC technique has been shown to reduce the latency and increase the data processing rates about 15％ In the results. Therefore, it seems reasonable to conclude that the parallel CRC realization in the RFID system offers a means of maintaining the integrity of data in the high speed RFID system.

• 전자공학회논문지
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• 제50권5호
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• pp.3-8
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• 2013

본 연구에서는 다중 안테나 시스템 기반 반복 수신기의 동작 원리를 이해하고 연산량을 줄이기 위한 연구를 진행하였다. 기존의 반복 수신기는 고정된 횟수의 반복 수신을 하는 것에 비하여, 적응형 반복 결정 방법은 프레임의 상태에 따라 반복 횟수를 조절함으로써 수신기에서의 불필요한 동작을 제한하여 연산량을 절감시킬 수 있다. 모의실험 결과를 통하여, 제안된 기법이 시스템의 에러 성능은 유지시키면서 수신기의 평균 반복 횟수를 크게 감소시키는 것을 확인하였다.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2005년도 한국컴퓨터종합학술대회 논문집 Vol.32 No.1 (A)
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• pp.460-462
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• 2005

본 논문은 통신 시스템에서 오류 검출을 위해 널리 사용되고 있는 Cyclic Redundancy Check (CRC)회로의 병렬 구현을 위한 최적화 알고리즘을 제시한다. 논리 단을 최소로 하면서 가능한 않은 공유 텀을 찾아 매핑 함으로써 속도 및 게이트 수를 줄인다. 본 논문에서는 이더넷의 32비트 CRC를 병렬로 구현하여 성능평가를 하였다. FPGA 및 표준 셀 라이브러리를 이용하여 합성하였으며, 기존의 방식에 비해 속도와 면적 모두 향상되었음을 보여준다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2009년도 춘계학술대회
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• pp.903-906
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• 2009

본 연구에서는 임베디드 시스템, 특히 블루투스 베이스밴드에서 사용이 가능한 고속 직렬 포트 인터페이스를 설계하였다. 인터페이스는 ARM 프로세서를 응용할 수 있는 AMBA APB에 호환될 수 있도록 설계하였으며, 8비트 형태로 외부 디바이스와 코프로세서 간 데이터와 명령을 전송할 수 있다. 오류 정정을 위하여, CRC를 적용하였고 멀티미디어 카드를 위한 인터페이스도 제공하였다. 설계한 직렬 포트 인터페이스는 자동합성하여 P&R을 수행하였다. 결과물은 Altera FPGA로 구현하였으며 25MHz에서 정상동작하였다.