• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.241-251
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• 2007

Energy consumption in the instruction cacheaccounts for a significant portion of the total processor energy consumption. Therefore, reducing energy consumption in the instruction cache is important in designing embedded processors. This paper proposes a method for reducing dynamic energy consumption in the instruction cache by partitioning it to smaller (less energy-consuming) sub-caches. When a request comes into the proposed cache, only one sub-cache is accessed by utilizing the locality of applications. By contrast, the other sub-caches are not accessed, leading todynamic energy reduction. In addition, the proposed cache reduces dynamic energy consumption by eliminating the energy consumed in tag matching. We evaluated the energy efficiency by running cycle accurate simulator, SimpleScalar. with power parameters obtained from CACTI. Simulation results show that the proposed cache reduces dynamic energy consumption by $37%{\sim}60%$ compared to the traditional direct-mapped instruction cache.

• Journal of Energy Engineering
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• v.5 no.1
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• pp.8-18
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• 1996

As a part of comprehensive IGCC process simulation, the thermal performance analysis was performed for coal gas firing combined power plant. The combined cycle analyzed consisted of il Texaco gasifier and a low temperature gas cleanup system for the gasification block and a GE 7FA gas turbine, a HRSG and steam turbine for the power block. A steady state simulator called ASPEN(Advanced System for Process Engineering) code was used to simulate IGCC processes. Composed IGCC configuration included air integration between ASU and gas turbine and steam integration between gasifier, gas clean up and steam turbine. The results showed 20% increase in terms of gas turbine power output(MWe) comparing with natural gas case based on same heat input. The results were compared with other study results which Bechtel Canada Inc. performed for Nova Scotia power plant in 1991 and the consistency was identified within two studies. As a result, the analysing method used in this study is verified as a sound tool for commercial IGCC process evaluation.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.8
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• pp.741-751
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• 2000

To achieve high performance by exploiting instruction level parallelism aggressively in superscalar processors, it is necessary to overcome the limitation imposed by control dependences and data dependences which prevent instructions from executing parallel. Value prediction is a technique that breaks data dependences by predicting the outcome of an instruction and executes speculatively its data dependent instruction based on the predicted outcome. In this paper, a hybrid value prediction scheme with dynamic classification mechanism is proposed. We design a hybrid predictor by combining the last predictor, a stride predictor and a two-level predictor. The choice of a predictor for each instruction is determined by a dynamic classification mechanism. This makes each predictor utilized more efficiently than the hybrid predictor without dynamic classification mechanism. To show performance improvements of our scheme, we simulate the SPECint95 benchmark set by using execution-driven simulator. The results show that our scheme effect reduce of 45% hardware cost and 16% prediction accuracy improvements comparing with the conventional hybrid prediction scheme and two-level value prediction scheme.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.72-72
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• 2018

A dynamic fatigue characteristic of dental implant system has been evaluated with applying single axial compressive shear loading based on the ISO 14801 standard. For the advanced dynamic fatigue test, multi-directional force and motion needed to be accompanied for more information of mechanical properties as based on mastication in oral environment. In this study, we have prepared loading and motion protocol for the multi-directional fatigue test of dental implant system with single (Apical/Occlusal; AO), and additional mastication motion (Lingual/Facial; LF, Mesial/Distal; MD). As following the prepared protocol (with modification of ISO 14801), fatigue test was conducted to verify the worst case results for the development of highly stabilized dental implant system. Mechanical testing was performed using an universal testing machine (MTS Bionix 858, MN, USA) for static compression and single directional loading fatigue, while the multi-directional loading was performed with joint simulator (ADL-Force 5, MA, USA) under load control. Basically, all mechanical test was performed according to the ISO 14801:2016 standard. Static compression test was performed to identify the maximum fracture force with loading speed of 1.0 mm/min. A dynamic fatigue test was performed with 40 % value of maximum fracture force and 5 Hz loading frequency. A single directional fatigue test was performed with only apical/occlusal (AO) force application, while multi directional fatigue tests were applied $2^{\circ}$ of facial/lingual (FL) or mesial/distal (MD) movement. Fatigue failure cycles were entirely different between applying single-directional loading and multi-directional loading. As a comparison of these loading factor, the failure cycle was around 5 times lower than single-directional loading while applied multi-directional loading. Also, the displacement change with accumulated multi-directional fatigue cycles was higher than that of single directional cycles.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.148-156
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• 2001

This paper proposed embedded application-specific microprocessor(YS-RDSP) whose structure has an additional DSP processor on chip. The YS-RDSP can execute maximum four instructions in parallel. To make program size shorter, 16-bit and 32-bit instruction lengths are supported in YS-RDSP. The YS-RDSP provides programmability. controllability, DSP processing ability, and includes eight-kilobyte on-chip ROM and eight-kilobyte RAM. System controller on the chip gives three power-down modes for low-power operation, and SLEEP instruction changes operation statue of CPU core and peripherals. YS-RDSP processor was implemented with Verilog HDL on top-down methodology, and it was improved and verified by cycle-based simulator written in C-language. The verified model was synthesized with 0.7um, 3.3V CMOS standard cell library, and the layout size was 10.7mm78.4mm which was implemented by using automatic P&R software.

• The Journal of the Korea Contents Association
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• v.7 no.3
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• pp.68-78
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• 2007

In a virtual aquarium, the behavior of fish objects is the most important factor in respect of visual effects. In addition to the individual behavior of fish object, the interactions between objects due to their attributes, can improve the dynamics and reality of the virtual world. In this paper, we analyze the principal habits of fish objects such as the vitality, the range of movement, the maximum depth of water they can live, and the cycle of eating. Then, we suggest a method for simulating the stable marine ecosystem with controlling the behaviors, the interaction with other species, the average span of life, and all that sort of thing based on the result of analysis. Because we can freely modify the behavior of fish object by altering the values of attributes, it can be utilized in the dynamic virtual aquarium, the 3D aquarium screen saver, and the virtual fish game, and so on.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2A
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• pp.80-85
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• 2003

This paper proposes Galois Field Arithmetic Unit(GFAU) whose structure does addition, multiplication and division in GF(2m). GFAU can execute maximum two additions, or two multiplications, or one addition and one multiplication. The base architecture of this GFAU is a divider based on modified Euclid's algorithm. The divider was modified to enable multiplication and addition, and the modified divider with the control logic became GFAU. The GFAU for GF(2193) was implemented with Verilog HDL with top-down methodology, and it was improved and verified by a cycle-based simulator written in C-language. The verified model was synthesized with Samsung 0.35um, 3.3V CMOS standard cell library, and it operates at 104.7MHz in the worst case of 3.0V, 85$^{\circ}C$, and it has about 25,889 gates.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.959-962
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• 2010

There are a lot of methods available in designing PID(Proportional-Integral-Derivative) and Lead/Lag controllers in the industrial field of technology because of their useful advantages such as simplicity and robustness. In an early stage of development process, a computational simulation approach is a very efficient tool for the designs of the controllers. Thus, in this paper we propose a cost-effective, and practically efficient. The PID and Lead/Lag controllers. To show the effectiveness of the proposed Lead/Lag controller, we compare and contrast of the simulation results of each controller with the Matlab simulator. Although we have only considered the DC motors for the controllers, but it could be extended in future developments to more complex plants. As a result, the proposed frameworks could be used to solve industrial problems such as a reduction in development cycle time and minimizing system errors.

• Clean Technology
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• v.24 no.4
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• pp.357-364
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• 2018

Studies on the production of biogas from third generation biomass, such as micro- and macroalgae, have been conducted through experiments of various scales. In this paper, we investigated the feasibility of commercialization of integrated combined heat and power (CHP) production using biogas derived from macroalgae, i.e., seaweed biomass. For this purpose, an integrated CHP plant of industrial scale, consisting of solid oxide fuel cells, gas turbine and organic Rankine cycle, was designed and simulated using a commercial process simulator. The cost of each equipment in the plant was estimated through the calculated heat and mass balances from simulation and then the techno-economic analysis was performed. The designed integrated CHP process produces 68.4 MW of power using $36ton\;h^{-1}$ of biogas from $62.5ton\;h^{-1}$ (dry basis) of brown algae. Based on these results, various scenarios were evaluated economically and the levelized electricity cost (LEC) was calculated. When the lifetime of SOFC is 5 years and its stack price is $$225kW^{-1}$, the LEC was 12.26 ¢ $kWh^{-1}$, which is comparable to the conventional fixed power generation.

• Journal of the Korea Society for Simulation
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• v.19 no.3
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• pp.81-89
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• 2010

Recent modeling and simulation technology is being used in various fields. Especially in the field of military, Simulation-Based Acquisition (SBA) is recognized as a essential policy. To effectively carry out SBA, modeling and simulation techniques should be applied in the whole life-cycle for the weapon system development, and simulation architecture framework which provides easily reusable and interoperability is needed. Through reusability and interoperability, the costs of constructing the integrated collaborate environment for simulation based acquisition can be minimized. In this study, we define requirements, issues for enhancing reusability and interoperability, and propose simulation framework as a solution of the problem including structural design. Proposing simulation framework provides common functions for producing simulator as reusable units and easily changeable structure on user's purpose. In addition, we provide the result for applying simulation framework to our project.