• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.655-658
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• 2005

Due to reduced device sizes and threshold voltages, leakage current becomes an important issue in CMOS design. In a CMOS combinational logic circuit, the leakage current in the standby state depends on the state of the inputs and thus can be minimized by applying an optimal input when the circuit is idling. In this paper, we present a New Input Vector Control algorithm, called Leakage Minimization by Input vector Control (LMIC) for minimal leakage power. This algorithm finds the minimal leakage vector and reduces leakage current up to 22.% on the average, for TSMC 0.18um process parameters. Minimal leakage vectors are very useful in reducing leakage currents in standby mode of operation.

• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.53-55
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• 2006

In this paper discusses winding methode of single phase AC-DC reversible power converter The reversible power converter driven by multi Tap winding at both side switching control. It has a advantage that simple drive of main switching device. and obtain load current of good quality without filter circuit and free from noise or isolation for lower switching frequency. In this research, study on current type converter and inverter circuit that consist for possibility of AC-DC/DC-AC multi-level reversible converter.

• Proceedings of the KIPE Conference
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• 2003.11a
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• pp.95-98
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• 2003

A ZVT PWM Boost Converter is proposed to reduce current stresses and conduction losses of main switch in a conventional circuit. By attaching resonant inductor Lr1 in parallel with capacitor Cr, the resonant circulating current is diverted to the additional component and then the main switch is subjected to minimum current stresses same as those in their PWM counterparts. Moreover, the operation of the auxiliary switch in a half wave mode to prevent reverse resonant energy from freewheeling can be able to lessen the conduction losses. The operation principles of the proposed converters are analyzed using the PWM boost converter topology as an example. Theoretically analysis and experimental results verify the validity of the boost converter topology with the proposed circuit.

• Electrical & Electronic Materials
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• v.9 no.10
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• pp.1019-1026
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• 1996

In this study, we may be presented the carrier oscillation properties for the low-voltage varistor fabricated by a new method of three composition seed grain, in order to analyze the behavior of carriers at the its equivalent circuit model. The oscillation phenomena of carriers appeared from current-voltage characteristics under knee voltage is shown by the transient flow of nontrapped carriers group in the trap level of intergranular layer, surface state and/or depletion layer. In particularly, current oscillation phenomena is hardly shown in the high electric field. It is that the injected carriers from both electrodes are directly from the conduction band of forward biased ZnO grain through the intergranular layer into the reverse biased ZnO grain, because the trap level in the electric field above the knee voltage is mostly filled.

• Journal of electromagnetic engineering and science
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• v.18 no.1
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• pp.1-6
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• 2018

In this study, the analytic expression for the positive/negative $n^{th}-Mode$ resonance frequency of an N unit cell composite right-/lefthanded (CRLH) transmission line is derived. To explain the resonance mechanism of the $n^{th}$ mode, especially for the negative mode, the current distribution of the N unit cell CRLH transmission line is investigated with a circuit simulation. Results show that both positive and negative $n^{th}$ resonance modes have n times current variations, but their phase difference is $180^{\circ}$ as expected. Moreover, the positive $n^{th}$ resonance occurs at a high frequency, whereas the negative $n^{th}$ resonance transpires at a low frequency, thus indicating that the negative resonance mode can be utilized for a small resonator. The correlation between the slope of the dispersion curve and the bandwidth is also observed. In sum, the balanced condition of the CRLH transmission line provides a broader bandwidth than the unbalanced condition.

• Proceedings of the KIPE Conference
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• 1998.07a
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• pp.39-42
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• 1998

This paper is presented the Partial Resonant Soft Switching Mode Power Converter which is adapted the power converter having the partial resonant soft switching mode, that makes switches operated when the resonant current or voltage becomes zero by making the resonant circuit partially at turning on and off of the switches with suitable layout of the resonant elements and switch elements in the converter. Also, this paper includes the analysis and simulation of the Partial Resonant type Buck-Boost Chopper.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.6
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• pp.494-501
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• 2006

In this paper, a novel energy recovery circuit for AC PDPs(Plasma Display Panels) with reduced sustain voltage is proposed to improve the performance of conventional circuits such as TERES(TEchnology of REciprocal Sustainer). In the TERES circuit, the sustain voltage is the half of general sustaining driver for AC PDPs, however, there is no energy recovery circuit. In the proposed circuit, the efficiency is heightened by installing in energy recovery circuit and the loss of switching device is reduced by performing the zero voltage switching or zero current switching. Although the energy recovery circuit is added, the number of active switching elements of the proposed circuit is the same as that of the TERES circuit. The operations of the proposed circuit are analyzed for each mode and its validity is verified by the simulations and experimentation.

• Journal of Electrical Engineering and Technology
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• v.9 no.1
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• pp.301-306
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• 2014

We proposed a new PCB-type 'common-mode current($I_c$) and differential-mode current($I_d$) detector' working for fast detection of $I_c$ and $I_d$ from the differential-mode signaling, with miniaturization effect and possibility of cheaper fabrication. In order to realize this device, we suggest a branch-line-coupler balun having a composite right- and left-handed(CRLH) one-layer microstrip phase-shifting line as compact as roughly ${\lambda}_g/14$. The presented balun obviously is different from the conventional bent-&-folded delay lines or slits on the ground for coupling the lines on the top and bottom dielectrics. As we connect the suggested balun output ports of the differential-mode signal lines via the through-port named U and coupled-port named L, $I_c$ and $I_d$ will appear at port ${\Delta}$ and port ${\Sigma}$ of the present device, in order. The validity of the design scheme is verified by the circuit-and numerical electromagnetic analyses, and the dispersion curve proving the metamaterial characteristics of the geometry. Besides, the examples of the $I_c$ and $I_d$ indicator are observed as the even and odd modes in differential-mode signal feeding. Also, the proposed device is shown to be very compact, compared with the conventional structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.79-85
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• 2009

The design of a 3.2 Gb/s serial link receiver in $0.18{\mu}m$ CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty. The design uses a multi-level signaling(4-PAM) to overcome these problems. Moreover, to increase data bit-rate and lower BER, we designed this circuit by using a current mode amplifier, Current-mode Logic(CML) sampling latches. The 4-PAM receiver achieves 3.2 Gb/s and BER is less than $1.0\;{\times}\;10^{-12}$. The $0.5\;{\times}\;0.6\;mm^2$ chip consumes 49 mA at 3.2 Gb/s from a 1.8-V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.98-104
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• 2006

The conventional burst-mode APC(Automatic Power Control) circuit had an effective structure that was suitable for a low power consumption and a monolithic chip. However, as data rate was increased, it caused errors due to the effect of the zero density. In this paper, we invented a new structured peak-comparator which could compensate the unbalance of the injected currents using double gated MOS and MOS diode. And we proposed a new burst-mode APC adopting it. The new peak-comparator in the proposed APC was very robust to zero density variations maintaining the correct decision point of the current comparison at high data rate. It was also suitable for a low power consumption and a monolithic chip due to lack of large capacitors.