• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.9
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• pp.576-583
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• 2004

This paper presents a buck circuit topology of high-frequency with a single switching device. It solved the problem which arised from hard-switching in high-frequency using a resonant snubber and operating under the principle of ZCS turn-on and ZVS turn-off commutation schemes. In the existing circuit, it has the voltage stress that is almost twice of input voltage in a free-wheeling diode. In the proposed circuit, it has the voltage stress that is lower than input voltage with modifing a location of free -wheeling diode. In this paper, it expained the circuit operation of each mode and analyzed feedback-loop stabilization. Also it confirmed the waveform of each mode with simulation result. The experiment result verified the simulation waveform and compared the voltage stress of a free -wheeling diode in the exsiting circuit with the voltage stress of that in the proposed circuit. Moreover, it compares and analyzes the proposed circuit's efficiency with the hard-switching circuit's efficiency according to the change of load current.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.5
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• pp.386-393
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• 2007

Charge-pump high voltage inverter for Plasma backlight using CIM(Current Injection Method) is proposed in this paper. Adoption of ERC(Energy Recovery Circuit) is a new attempt in high voltage inverter so that it is not only energy recovery but also improvement of discharge stability and system unstability which is interrupted by noise. Using a charge-pump technique enables low voltage switches to be usable, the cost can be reduced. CIM is adopted to achieve high speed energy recovery in proposed circuit. Operations of the proposed circuit are analyzed for each mode. The proposed circuit is verified to be applicable on a 32 inch plasma backlight panel by experimental results.

• Journal of Electrical Engineering and Technology
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• v.6 no.1
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• pp.104-110
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• 2011

High-brightness LED control is required for stable operation, thus the driver and control system must be designed to deliver a constant current to optimize reliability and ensure consistent luminous flux. In this paper, the sliding mode current controller is designed to adjust the illumination density of power LEDs. The controller design model of power LEDs, including its driving circuit, is proposed to realize the dimming control of power LEDs. A buck converter is introduced to drive the power LEDs and reduce the input voltage to a lower level. The sliding mode software controller is implemented to adjust the dimming of power LEDs. The proposed strategy for driving power LEDs is investigated and comparatively studied by experiments.

• Journal of Aerospace System Engineering
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• v.14 no.6
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• pp.79-84
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• 2020

Cooler driver electronics (CDE) for maintaining low temperature of the satellite payload IR sensor consists of a compressor that has a pulsation current load condition when it is operated. This pulsation current produces large voltage fluctuation, which affects both load and regulated bus stability. Thus, CDE power conditioning system consists of a primary bus, infrared power distribution unit for battery charging and protection, reverse current protection diode, and battery, which is used as a buffer. In this study, the operational mode analysis is performed by each part with equivalent impedance modeling verified through system level simulation. From this mode analysis, the safety margin for state of charge and open circuit voltage of the battery is determined for satisfying the minimum operational voltage of the CDE load.

• The Journal of the Korea Contents Association
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• v.6 no.3
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• pp.38-45
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• 2006

A dual-level low voltage differential signalling (DLVDS) circuit is proposed aiming at reducing transmission lines for a LCD driver IC. We apply two data to the proposed DLVDS circuit as inputs. Then, the transmitter converts two inputs to two kinds of fully differential signals. In this circuit, two transmission lines are sufficient to transfer two inputs while keeping the LVDS feature. However, the circuit has a common mode bias fluctuation due to difference of the input bias and the reference bias. We compensate the common mode bias fluctuation using a feedback circuit of the current source bias. The receiver recovers the original input data through a level decoding circuit. We fabricated the proposed circuit using $0.25{\mu}m$ CMOS technology. The simulation results of proposed circuit shows 1-Gbps/2-line data rate and 35mW power consumption at 2.5V supply voltage, respectively.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1038-1040
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• 1993

Single phase AC to DC Boost-converter which is control led with a variable hysteretic current mode for improvent of input power factor makes high power factor possible. Power Factor correction circuit can be identified with a determination of each parameters. A simaluation and experiment result to load and parameter variation is examined.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.2
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• pp.248-255
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• 2009

Error is the major problem in communication system. Absolute circuit is one of the most important building blocks to implement for the error measurement in communication system as well as in analog circuit design. The main goal of this paper is to design a circuit with high accuracy and minimum error performance. In this paper, a new current mode absolute circuit is implemented to calculate the absolute value of two signals. This new design shows enhanced performance and low distortion over the previous implementation. The proposed circuit is simulated using Hspice and implemented in analog viterbi decoder. It is very suitable for implementing in error calculation for the large scale integrated circuit. Hspice simulation results of previous and new one circuit are reported.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.72-79
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• 2003

Classical designs of optical transimpedance preamplifier for p-i-n photodiode receiver circuits generally employ common source transimpedance input stages. In this paper, we explore the design of a class of current-mode optical transimpedance preamplifier based upon common gate input stages. A feature of current-mode optical transimpedance preamplifier is high gain and high bandwidth. The bandwidth of the transimpedance preamplifier can also be increased by the capacitive peaking technique. In this paper we included the development and application of a circuit analysis technique based on the minimum noise. We develop a general formulation of the technique, illustrate its use on a number of circuit examples, and apply it to the design and optimization of the low-noise transimpedance amplifier. Using the noise minimization method and the capacitive peaking technique we designed a transimpedance preamplifier with low noise, high-speed current-mode transimpedance preamplifier with a 1.57GHz bandwidth, and a 2.34K transimpedance gain, a 470nA input noise current. The proposed preamplifier consumes 16.84mW from a 3.3V power supply.

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.1-6
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• 2005

This paper proposes a high performance multiplier using CMOS multiple-valued logic circuits. The multiplier based on the Modified Baugh-Wooley algorithm is designed with current-mode CMOS quaternary logic circuits. The multiplier is functionally partitioned into the following major sections: partial product generator block(binary-quaternary logic conversion block), current-mode quaternary logic full-adder block, and quaternary-binary logic conversion block. The proposed multiplier has 4.5ns of propagation delay and 6.1mW of power consumption. This multiplier can easily adapted to the binary system by the encoder and the decoder. This circuit is designed with 0.35um standard CMOS process at 3.3V supply voltage and 5uA unit current. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of Sensor Science and Technology
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• v.28 no.5
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• pp.284-288
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• 2019

A calibration-free analog neuron circuit is proposed as a viable alternative to the power hungry digital neuron in implementing a deep neural network. The conventional analog neuron requires calibrations because a voltage-mode link is used between the soma and the synapse, which results in significant uncertainty in terms of current mapping. In this work, a current-mode link is used to establish a robust link between the soma and the synapse against the variations in the process and interconnection impedances. The increased hardware owing to the adoption of the current-mode link is estimated to be manageable because the number of neurons in each layer of the neural network is typically bounded. To demonstrate the utility of the proposed analog neuron, a simple neural network with $4{\times}7{\times}3$ architecture has been designed for classifying iris flowers. The chip is now under fabrication in 0.35 mm CMOS technology. Thus, the proposed true current-mode analog neuron can be a practical option in realizing power-efficient neural networks for edge computing.