• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.4
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• pp.685-695
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• 1997

In this paper, a new CMOS continuous-time fully-differential current-mode integrator is proposed as a basic building block of the low-voltage high frequency current-mode active filter. The proposed integrator is composed of the CMOS complementary circuit which can extend transconductance of an integrator. Therefore, the unity gain frequency which is determined by a small-signal transconductance and a MOSFET gate capacitance can be expanded by the complementary transconductance of the proposed integrator. And also the magnitude of pole and zero are increased. The unity gain frequency of the proposed integrator is increased about two times larger than that of the conventional continuous-time fully-differential integrator with NMOS-gm. These results are verified by the small signal analysis and the SPICE simulation. As an application circuit of the proposed fully-differential current-mode integrator, the three-pole Chebyshev lowpass filter is designed using 0.8.$\mu$m CMOS processing parameters. SPICE simulation predicts a 3-dB bandwidth of 148MHz and power dissipation of 4.3mW/pole for the three-pole filter with 3-V power supply.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.151-154
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• 2001

This paper propose a new active common-mode voltage damper circuit that is capable of suppressing a common-mode voltage produced in the PWM VSI. The new active common mode voltage damper is consisted of a half-bridge inverter and a common mode transformer with a blocking capacitor. Principle of the active common mode damper is as follow; by applying the compensation voltage which has the same amplitude and opposite polarity to the PWM inverter system. So, common mode voltage and high frequency leakage current can be reduced. Simulated and experimental results show that common-mode voltage damper makes contributions to reducing a high frequency leakage current and common-mode voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.9
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• pp.1693-1698
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• 2015

This paper proposed a PFM(pulse-frequency modulator) boost converter which has dual pulse-width. The PFM boost converter is composed of BGR(band gap voltage reference generating circuit), voltage reference generating circuit, soft-start circuit, error amplifier, high-speed comparator, inductor current sensing circuit and pulse-width generator. Converter has different inductor peak current so it has wider load current range and smaller output voltage ripple. Proposed PFM boost converter generates 18V output voltage with input voltage of 3.7V and it has load current range of 0.1~300mA. Simulation results show 0.43% output voltage ripple at ligh load mode and 0.79% output voltage ripple at heavy load mode. Converter has efficiency 85% at light lode mode and it has maximum 86.4% at 20mA load current.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.493-498
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• 2004

The EMI noise source in a switching mode power supply is dominated by a common mode noise. If we can understand the common mode noise occurring mechanism, it is resulted to find out the method to suppress the EMI noise source in the switching mode power supply. The common mode noise is occurring mostly due to circuit is unbalanced which is caused by the capacitive coupling to frame ground, which passes through a heatsink of the switching devices. This research paper presents a new effective balancing method of buck converter circuit by mean of grounding the parasitic and compensation capacitors in correct proportion which is called that the common mode impedance balance (CMIB). The CMIB can be achieved by source, transmission line and termination balanced, such balancing, the common mode current will be cancelled out in the frame ground. The greatly reduced common mode noise can be confirmed by the experimental results.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.8
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• pp.45-51
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• 2008

HID(High Intensity Discharge) search lamp for shipment requires a high open circuit and output current compare than vehicle. This paper presents a soft-start open circuit voltage and constant current sequence control method for 2.5[kW] HID search lamp. The proposed method controls the opal circuit voltage and discharge current of HID lamp according to ignition signal with a simple 8-bit micro-processor and PWM device. For the stable control of lamp, micro-processor checks the output voltage and current. And the checked signals are compared with ignition signal and changes the control mode for stable operation. An ignition signal and micro-processor change the control mode from open circuit voltage contort to constant current control. The proposed control scheme is verified from experimental tests of 2.5[kW] HID search lamp for shipment.

• Journal of Sensor Science and Technology
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• v.32 no.6
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• pp.432-440
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• 2023

This study introduces an efficient readout circuit designed for two-electrode electrocardiogram (ECG) recording, characterized by its low-noise and low-power consumption attributes. Unlike its three-electrode counterpart, the two-electrode ECG is susceptible to common-mode interference (CMI), causing signal distortion. To counter this, the proposed circuit integrates a common-mode charge pump (CMCP) with a window comparator, allowing for a CMI tolerance of up to 20 V_PP. The CMCP design prevents the activation of electrostatic discharge (ESD) diodes and becomes operational only when CMI surpasses the predetermined range set by the window comparator. This ensures power efficiency and minimizes intermodulation distortion (IMD) arising from switching noise. To maintain ECG signal accuracy, the circuit employs a chopper-stabilized instrumentation amplifier (IA) for low-noise attributes, and to achieve high input impedance, it incorporates a floating high-pass filter (HPF) and a current-feedback instrumentation amplifier (CFIA). This comprehensive design integrates various components, including a QRS peak detector and serial peripheral interface (SPI), into a single 0.18-㎛ CMOS chip occupying 0.54 mm². Experimental evaluations showed a 0.59 µV_RMS noise level within a 1-100 Hz bandwidth and a power draw of 23.83 µW at 1.8 V.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.626-630
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• 1999

A new integrated single-stage zero current switched(ZCS) quasi-resonant converter (QRC) for the power factor correction(PFC) converter is introduced in this paper. The power factor correction can be achieved by the discontinuous conduction mode(DCM) operation of an input current. The proposed converter has the characteristics of the good power factor, low line current harmonics, and tight output regulation. Furthermore, the ringing effect due to the output capacitance of the main switch can be eliminated by use of active clamp circuit.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.5
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• pp.388-392
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• 2012

In this paper, a sampler model for the P-type current mode control employing low pass filter is proposed. Even though the frequency response of the compensator used in a P-type current mode control employing low pass filter is similar to that of P-type compensator, the sampler model has to be obtained from the method used in PI-type current mode control. In order to show the usefulness of the proposed method, prediction results of the proposed model are compared to those from the circuit level simulator, PSIM.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.4
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• pp.137-142
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• 2023

When designing a SMPS(Switched Mode Power Supply) circuit, a part that is easily overlooked without special consideration is a snubber circuit. However, the performance degradation of the SMPS due to the snubber circuit and the effect on the entire SET cannot be ignored. In addition, a snubber circuit is added to both ends of the switch to protect the device from peak voltage and current during switching and to reduce loss during on/off switching. Therefore, in this paper, for a sufficient understanding of snubber circuits, theoretical analysis and experimental formulas that can be applied by designers during actual circuit design are arranged to promote optimization of snubber circuits.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2007.04a
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• pp.485-488
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• 2007

최근 Analog Sampled-Data 신호처리를 위하여 주목되고 있는 SI(Switched-Current) circuit은 저전력 동작을 하는 장점이 있지만, 반면에 SI circuit에서의 기본 회로인 Current Memory는 Charge Injection에 의한 Clock Feedthrough이라는 치명적인 단점을 갖고 있다. 따라서 본 논문에서는 Current Memory의 문제점인 Clock Feedthrough의 일반적인 해결방안으로 Dummy Switch의 연결을 검토하였고, Austria Mikro Systeme(AMS)에서 $0.35{\mu}m$ CMOS process BSIM3 Model로 제작하기 위하여 Current Memory의 Switch MOS와 Dummy Switch MOS의 적절한 Width을 정의하여야 하므로, 그 값을 도출하였다. Simulation 결과, Switch의 Width는 $2{\mu}m$, Dummy Switch의 Width는 $2.35{\mu}m$로 정의될 수 있음을 확인하였다.