• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제54권11호
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• pp.540-546
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• 2005

This paper presents a boost circuit topology driving in high - frequency It solves the problem which arised from hard-switching in high-frequency using a period of resonant circuit and operating under the principle of ZCS turn-on and ZCZVS turn-off commutation schemes. In the existing circuit, it has the high voltage and current stress in free- wheeling diode. But in the proposed circuit, it has voltage and current stress which is lower than voltage and current stress of existing circuit with modifing a location of free-wheeling diode. In this paper, it explained the circuit operation of each mode and the waveform of each mode. Also the experiment results compare the voltage and current stress of free-wheeling diode in the existing circuit with the voltage and current stress of that in the proposed circuit. Moreover, it compares and analyzes the proposed circuit's efficiency with the existing circuit's efficiency according to the change of load current.

• Journal of Power Electronics
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• 제12권3호
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• pp.399-409
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• 2012

In DC-DC Buck converters with average current mode control, the current loop compensator provides additional design freedom to enhance the converter current loop performance. On the other hand, the current loop circuit elements append substantial amount of complexity to not only the inner current loop but also the outer voltage loop, which makes it demanding to quantify circuit and operating parameter effects on the small-signal dynamics of such converters. Despite the difficulty, it is shown in this paper that parameter effects can be analyzed satisfactorily by using an existing small-signal model in conjunction with a newly proposed simplified alternative. As a result of the study, new insight into average current mode control is uncovered and discussed quantitatively. Measurable experimental results on a prototype averaged-current-mode-controlled Buck converter are provided to facilitate the analytical study with good correlation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.419-422
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• 2004

A sensing scheme for current-mode magneto-resistance random access memory (MRAM) with a 1T1MTJ cell structure is proposed. Magnetic tunnel junction (MTJ) resistance, which is HIGH or LOW, is converted to different cell currents during READ operation. The cell current is then amplified to be evaluated by the reference cell current. In this scheme, conventional bit line sense amplifiers are not required and the operation is less sensitive to voltage noise than that of voltage-mode circuit is. It has been confirmed with HSPICE simulations using a 0.35-${\mu}m$ 2-poly 4-metal CMOS technology.

• 전기전자학회논문지
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• 제18권4호
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• pp.586-592
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• 2014

본 논문에서는 DT-CMOS(Dynamic Threshold voltage Complementary MOSFET) 스위칭 소자를 사용한 DC-DC Buck 컨버터를 제안하였다. 높은 효율을 얻기 위하여 PWM 제어방식을 사용하였으며, 낮은 온 저항을 갖는 DT-CMOS 스위치 소자를 설계하여 도통 손실을 감소시켰다. 제안한 Buck 컨버터는 밴드갭 기준 전압 회로, 삼각파 발생기, 오차 증폭기, 비교기, 보상 회로, PWM 제어 블록으로 구성되어 있다. 삼각파 발생기는 전원전압(3.3V)부터 접지까지 출력 진폭의 범위를 갖는 1.2MHz의 주파수를 생성하며, 비교기는 2단 증폭기로 설계되었다. 그리고 오차 증폭기는 70dB의 이득과 $64^{\circ}$의 위상여유를 갖도록 설계하였다. 또한 제안한 Buck 컨버터는 current-mode PWM 제어회로와 낮은 온 저항을 갖는 스위치를 사용하여 100mA의 출력 전류에서 최대 95%의 효율을 구현하였으며, 1mA 이하의 대기모드에도 높은 효율을 구현하기 위하여 LDO 레귤레이터를 설계하였으며, 또한 2개의 IC 보호 회로를 내장하여 신뢰성을 확보하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.810-817
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• 2014

An on-chip current sensor with fast response time for the peak-current-mode buck regulator is proposed. The initial operating points of the peak current sensor are determined in advance by the valley current level, which is sensed by a valley current sensor. As a result, the proposed current sensor achieves a fast response time of less than 20 ns, and a sensing accuracy of over 90%. Applying the proposed current sensor, the peak-current-mode buck regulator for the mobile application is realized with an operating frequency of 2 MHz, an output voltage of 0.8 V, a maximum load current of 500 mA, and a peak efficiency of over 83%.

• 전기전자학회논문지
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• 제21권4호
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• pp.375-380
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• 2017

A differential current-to-time interval converter is presented for current mode sensors. It consists of a ramp voltage generator, a current mode sensor, a reference current source, two current-tunable Schmitt triggers, a one-shot multivibrator, and two logic gates. The design principle is to apply a ramp voltage to each input of the two current-tunable Schmitt triggers whose threshold voltages are proportional to the drain current values of the current mode sensors. A proposed circuit converts a current change in the ISFET biosensor into its equivalent pulse width change. A prototype circuit built using TSMC 0.18 nm CMOS process exhibit a conversion sensitivity amounting to $726.9{\mu}s/pH$ over pH variation range of 2-12 and a linearity error less than ${\pm}0.05%$.

• ETRI Journal
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• 제28권4호
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• pp.486-494
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• 2006

Two current-mode and/or voltage-mode quadrature oscillator circuits each using one fully-differential second-generation current conveyor (FDCCII), two grounded capacitors, and two (or three) grounded resistors are presented. In the proposed circuits, the current-mode quadrature signals have the advantage of high-output impedance. The oscillation conditions and oscillation frequencies are orthogonally (or independently) controllable. The current-mode and voltage-mode quadrature signals can be simultaneously obtained from the second proposed circuit. The use of only grounded capacitors and resistors makes the proposed circuits ideal for integrated circuit implementation. Simulation results are also included.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.200-203
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• 2002

This paper presents Continuous-current mode of $S^4$-PFC(Single-Stage Single-switch Power Factor Correction) converter. Proposed converter operates in the continueous current mode(CCM) at full load and discontinuous current mode(DCM) at light load. So, characteristic of proposed converter is no bus voltage stress and Zero Voltage Switching(ZVS) using resonant auxiliary circuit. And. This paper presents characteristic of $S^4$-PFC converter and effect of circuit parameter of proposed converter through the input inductor, PFC capacitor's variation. All of these theory and characteristic verified through the experiment with a 72W(12V, 6A), $90^{kHz}$ prototype converter.

• 전기전자학회논문지
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• 제11권2호
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• pp.83-88
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• 2007

이 논문은 MOS 전류모드 논리 (MOS current-mode logic circuit, MCML) 회로를 이용하여 저 전력 특성을 갖는 8${\times}$8 비트 병렬 곱셈기를 설계하였다. 이 8${\times}$8 병렬 곱셈기는 제안한 MCML 구조의 전가산기와 기존의 전가산기를 이용하여 설계하였다. 설계한 곱셈기는 기존 곱셈기에 비해 전력소모에서 9.4% 감소하였으며, 전력소모와 지연시간의 곱에서 11.7%의 성능향상이 있었다. 이 회로는 삼성 0.35${\mu}m$ 표준 CMOS 공정을 이용하여 설계하였으며, HSPICE를 통하여 검증하였다.

• 대한전자공학회논문지SD
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• 제40권11호
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• pp.37-44
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• 2003

다수의 입력을 필요로 하는 전류모드 Max 회로에서 고주파 왜곡을 효과적으로 억제할 수 있는 trans conductance 조정 방법을 제안하였다. Max 회로에 인가되는 입력 신호의 개수가 증가하면, 기생 커패시턴스는 입력 단의 개수에 비례하여 누적되게 된다. 본 연구에서는 Max 회로의 왜곡 신호의 크기가 누적된 기생 커패시턴스와 출력신호의 변화율에 비례하며, 공통 다이오드결선 트랜지스터의 transconductance 값에 반비례하게 됨을 밝혔다. 왜곡 억제를 위한 효과적인 방안으로 공통 다이오드결선 트랜지스터의 transconductance 값을 최소화하는 방안을 제시하였다. 이 방법의 효용성은 다양한 수의 입력 신호를 갖는 전류모드 Max 회로에 대해서 HSPICE 시뮬레이션을 통해 입증하였다.