• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.11
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• pp.540-546
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• 2005

This paper presents a boost circuit topology driving in high - frequency It solves the problem which arised from hard-switching in high-frequency using a period of resonant circuit and operating under the principle of ZCS turn-on and ZCZVS turn-off commutation schemes. In the existing circuit, it has the high voltage and current stress in free- wheeling diode. But in the proposed circuit, it has voltage and current stress which is lower than voltage and current stress of existing circuit with modifing a location of free-wheeling diode. In this paper, it explained the circuit operation of each mode and the waveform of each mode. Also the experiment results compare the voltage and current stress of free-wheeling diode in the existing circuit with the voltage and current stress of that in the proposed circuit. Moreover, it compares and analyzes the proposed circuit's efficiency with the existing circuit's efficiency according to the change of load current.

• Journal of Power Electronics
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• v.12 no.3
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• pp.399-409
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• 2012

In DC-DC Buck converters with average current mode control, the current loop compensator provides additional design freedom to enhance the converter current loop performance. On the other hand, the current loop circuit elements append substantial amount of complexity to not only the inner current loop but also the outer voltage loop, which makes it demanding to quantify circuit and operating parameter effects on the small-signal dynamics of such converters. Despite the difficulty, it is shown in this paper that parameter effects can be analyzed satisfactorily by using an existing small-signal model in conjunction with a newly proposed simplified alternative. As a result of the study, new insight into average current mode control is uncovered and discussed quantitatively. Measurable experimental results on a prototype averaged-current-mode-controlled Buck converter are provided to facilitate the analytical study with good correlation.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.419-422
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• 2004

A sensing scheme for current-mode magneto-resistance random access memory (MRAM) with a 1T1MTJ cell structure is proposed. Magnetic tunnel junction (MTJ) resistance, which is HIGH or LOW, is converted to different cell currents during READ operation. The cell current is then amplified to be evaluated by the reference cell current. In this scheme, conventional bit line sense amplifiers are not required and the operation is less sensitive to voltage noise than that of voltage-mode circuit is. It has been confirmed with HSPICE simulations using a 0.35-${\mu}m$ 2-poly 4-metal CMOS technology.

• Journal of IKEEE
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• v.18 no.4
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• pp.586-592
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• 2014

In this paper, high efficiency power management IC(PMIC) with DT-CMOS(Dynamic threshold voltage Complementary MOSFET) switching device is presented. PMIC is controlled PWM control method in order to have high power efficiency at high current level. The DT-CMOS switch with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuit consist of a saw-tooth generator, a band-gap reference(BGR) circuit, an error amplifier, comparator circuit, compensation circuit, and control block. The saw-tooth generator is made to have 1.2MHz oscillation frequency and full range of output swing from supply voltage(3.3V) to ground. The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on current mode PWM control circuits and low on-resistance switching device, achieved the high efficiency nearly 96% at 100mA output current. And Buck converter is designed along LDO in standby mode which fewer than 1mA for high efficiency. Also, this paper proposes two protection circuit in order to ensure the reliability.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.810-817
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• 2014

An on-chip current sensor with fast response time for the peak-current-mode buck regulator is proposed. The initial operating points of the peak current sensor are determined in advance by the valley current level, which is sensed by a valley current sensor. As a result, the proposed current sensor achieves a fast response time of less than 20 ns, and a sensing accuracy of over 90%. Applying the proposed current sensor, the peak-current-mode buck regulator for the mobile application is realized with an operating frequency of 2 MHz, an output voltage of 0.8 V, a maximum load current of 500 mA, and a peak efficiency of over 83%.

• Journal of IKEEE
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• v.21 no.4
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• pp.375-380
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• 2017

A differential current-to-time interval converter is presented for current mode sensors. It consists of a ramp voltage generator, a current mode sensor, a reference current source, two current-tunable Schmitt triggers, a one-shot multivibrator, and two logic gates. The design principle is to apply a ramp voltage to each input of the two current-tunable Schmitt triggers whose threshold voltages are proportional to the drain current values of the current mode sensors. A proposed circuit converts a current change in the ISFET biosensor into its equivalent pulse width change. A prototype circuit built using TSMC 0.18 nm CMOS process exhibit a conversion sensitivity amounting to $726.9{\mu}s/pH$ over pH variation range of 2-12 and a linearity error less than ${\pm}0.05%$.

• ETRI Journal
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• v.28 no.4
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• pp.486-494
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• 2006

Two current-mode and/or voltage-mode quadrature oscillator circuits each using one fully-differential second-generation current conveyor (FDCCII), two grounded capacitors, and two (or three) grounded resistors are presented. In the proposed circuits, the current-mode quadrature signals have the advantage of high-output impedance. The oscillation conditions and oscillation frequencies are orthogonally (or independently) controllable. The current-mode and voltage-mode quadrature signals can be simultaneously obtained from the second proposed circuit. The use of only grounded capacitors and resistors makes the proposed circuits ideal for integrated circuit implementation. Simulation results are also included.

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.200-203
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• 2002

This paper presents Continuous-current mode of $S^4$-PFC(Single-Stage Single-switch Power Factor Correction) converter. Proposed converter operates in the continueous current mode(CCM) at full load and discontinuous current mode(DCM) at light load. So, characteristic of proposed converter is no bus voltage stress and Zero Voltage Switching(ZVS) using resonant auxiliary circuit. And. This paper presents characteristic of $S^4$-PFC converter and effect of circuit parameter of proposed converter through the input inductor, PFC capacitor's variation. All of these theory and characteristic verified through the experiment with a 72W(12V, 6A), $90^{kHz}$ prototype converter.

• Journal of IKEEE
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• v.11 no.2
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• pp.83-88
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• 2007

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The 8${\times}$8 multiplier is designed with proposed MCML full adders and conventional full adders. The designed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. This circuit is designed with Samsung 0.35${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.37-44
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• 2003

A distortion suppression technology for employing multiple inputs in 3n＋1 type current mode Max circuit is proposed using the adjustment of transconductance. If the number of input blocks of the current mode Max circuit increases, the high frequency distortion in the output signal grows. In this paper, it has been disclosed that the distortion in the multiple input Max circuit is proportional to such accumulated parasitic capacitance, to the derivative of the output signal and also to tile inverse of transconductance of the common diode-connected transistor. The proposed idea is by employing as larger transconductance of the common diode-connected transistor as possible. The effectiveness of the proposed idea has been proved through the HSPICE simulation for the current mode Max circuits with various numbers of input signals.