• 전력전자학회논문지
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• 제27권2호
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• pp.134-141
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• 2022

This study presents a method for reducing current distortion that occurs when a dual-buck inverter generates reactive power. Dual-buck inverters, which are only capable of unity power factor operation, can generate reactive power capabilities by modifying a modulation technique. However, under non-unity power factor conditions, current distortion occurs at zero-crossing points of grid voltage and output current. This distortion is caused by parasitic capacitors, dead-time, and discontinuous conduction mode operation. This study proposes a modified modulation method to alleviate the current distortion at zero-crossing point of the grid voltage. A repetitive controller is applied to reduce this distortion of the output current. A 1 kVA prototype is built and tested. Simulation and experimental results demonstrate the effectiveness of the proposed method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 F
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• pp.2204-2206
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• 1997

A novel zero voltage and zero current switching (ZVZCS) full bridge (FB) PWM converter with a low output current ripple is proposed. The proposed circuit improve the demerits of the previously presented ZVBCS-FB-PWM converters[5-8] such as use of lossy components or additional active switches. A simple auxiliary circuit which includes neither lossy components nor active switches provides ZVZCS conditions to primary switches, ZVS for leading-leg switches and ZCS for lagging-leg switches. In addition, this proposed circuit reduces a output current ripple considerably. Many advantages including simple circuit topology, high efficiency, low cost and low current ripple make the new converter attractive far high power (> 1kW) applications.

• Journal of Power Electronics
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• 제12권4호
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• pp.528-537
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• 2012

This paper presents an interleaved resonant converter with a parallel-series transformer connection in order to achieve ripple current reduction at the output capacitor, zero voltage turn-on for the active switches, zero current turn-off for the rectifier diodes, less voltage stress on the rectifier diodes, and less current stress on the transformer primary windings. The primary windings of the two transformers are connected in parallel in order to share the input current and to reduce the root-mean-square (rms) current on the primary windings. The secondary windings of the two transformers are connected in series in order to ensure that the transformer primary currents are balanced. A full-wave diode rectifier is used at the output side to clamp the voltage stress of the rectifier diode at the output voltage. Two circuit modules are operated with the interleaved PWM scheme so that the input and output ripple currents are reduced. Based on the resonant behavior, all of the active switches are turned on under zero voltage switching (ZVS), and the rectifier diodes are turned off under zero current switching (ZCS) if the operating switching frequency is less than the series resonant frequency. Finally, experiments with a 1kW prototype are described to verify the effectiveness of the proposed converter.

• 전력전자학회논문지
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• 제20권4호
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• pp.321-329
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• 2015

The static synchronous compensator (STATCOM) of cascaded H-bridge configuration accompanying multiple separate DC sides is inherently subject to the problem of uneven DC voltages. These DC voltages in one leg can be controlled by adjusting the AC-side output voltage of each cell inverter, which is proportional to the active power. However, when the phase current is extremely small, large AC-side voltage is required to generate the active power to balance the cell voltages. In this study, an alternative zero-sequence current injection method is proposed, which facilitates effective cell balancing controllers at no load, and has no effect on the power grid because the injected zero sequence current only flows within the STATCOM delta circuit. The performance of the proposed method is verified through simulation and experiments.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• 제4B권3호
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• pp.127-133
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• 2004

This paper presents a prototype of three-phase current source zero voltage soft-switching PWM controlled PFC rectifier with Single Active Auxiliary Resonant Commutated Snubber (ARCS) circuit topology. The proposed three-phase PFC rectifier with sinewave current shaping and unity power factor scheme can operate under a condition of Zero Voltage Soft Switching (ZVS) in the main three phase rectifier circuit and zero current soft switching (ZCS) in auxiliary snubber circuits. The operating principle and steady-state performances of the proposed three-phase current source soft-switching PWM controlled PFC rectifier controlled by the DSP control implementation are evaluated and discussed on the basis of the experimental results of this active rectifier setup.

• Journal of Power Electronics
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• 제17권1호
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• pp.41-55
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• 2017

This study proposes a novel zero voltage transition (ZVT) pulse width modulation (PWM) DC-DC interleaved boost converter with an active snubber cell. All the semiconductor devices in the converter turn on and off with soft switching to reduce the switching power losses and improve the overall efficiency. Through the interleaved approach, the current stresses of the main devices and the ripple of the output voltage and input current are reduced. The main switches turn on with ZVT and turn off with zero voltage switching (ZVS). The auxiliary switch turns on with zero current switching (ZCS) and turns off with ZVS. In addition, the snubber cell does not create additional current or voltage stress on the main switches and main diodes. The proposed converter can smoothly achieve soft switching characteristics even under light load conditions. The theoretical analysis and operating stages of the proposed converter are made for the D > 50% and D < 50% modes. Finally, a prototype of the proposed converter is implemented, and the experimental results are given in detail for 500 W and 50 kHz. The overall efficiency of the proposed converter reached 95.5% at nominal output power.

• Journal of Power Electronics
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• 제15권4호
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• pp.1131-1138
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• 2015

This study presents an input-powered high-efficiency interface circuit for energy harvesting systems, and introduces a zero standby power design to reduce power consumption significantly while removing the external power supply. This interface circuit is composed of two stages. The first stage voltage doubler uses a positive feedback control loop to improve considerably the conversion speed and efficiency, and boost the output voltage. The second stage active diode adopts a common-grid operational amplifier (op-amp) to remove the influence of offset voltage in the traditional comparator, which eliminates leakage current and broadens bandwidth with low power consumption. The system supplies itself with the harvested energy, which enables it to enter the zero standby mode near the zero crossing points of the input current. Thereafter, high system efficiency and stability are achieved, which saves power consumption. The validity and feasibility of this design is verified by the simulation results based on the 65 nm CMOS process. The minimum input voltage is down to 0.3 V, the maximum voltage efficiency is 99.6% with a DC output current of 75.6 μA, the maximum power efficiency is 98.2% with a DC output current of 40.4 μA, and the maximum output power is 60.48 μW. The power loss of the entire interface circuit is only 18.65 μW, among which, the op-amp consumes only 2.65 μW.

• 전기학회논문지
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• 제57권6호
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• pp.972-981
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• 2008

A New ZVS(Zero Voltage Switching) and ZVZCS(Zero Voltage and Zero Current Switching) Three-Level Converter is proposed. The proposed converter presented in this paper used a phase shift control with a flying capacitor in the primary side to achieve ZVS for the all switch. A primary auxiliary circuit, which consists of one coupled inductor, is added in the primary to provide ZVZCS conditions to primary switches. Many advantages including simple circuit topology high efficiency, and low cost make this converter attractive for high power applications. The principle of operation, feature and design considerations are illustrated and verified through the experiment with a 2kW(27V, 74A) 40 kHz IGBT based experimental circuit.

• 전력전자학회논문지
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• 제27권5호
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• pp.431-437
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• 2022

This study proposes a converter that makes battery charging, discharging, and zero voltage control possible. The proposed topology consists of an LLC converter and a half-bridge inverter, and all power semiconductor devices are applied Si-MOSFETs. The topology is designed with an LLC switching frequency of 100 kHz, a half-bridge inverter switching frequency of 50 kHz, and a battery voltage of 5 V. The advantages of the charging/discharging operation of the 5 V battery voltage and the zero voltage control of the battery are verified. In addition, by using a two-stage topology, the battery can be charged, discharged through current control, and discharged to zero voltage. With the proposed topology, the current can be maintained even when the battery voltage drops to zero.

• Journal of Power Electronics
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• 제18권2호
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• pp.502-510
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• 2018

A circulating current is a major problem caused by directly connecting voltage-source inverters (VSIs) in parallel. This circulating current occurs as a zero-sequence current between the inverters by specific switch states. Several studies have presented alternatives using hardware and software methods. When coupled inductors (CIs) are employed for the high-frequency circulating current, a controller is required to prevent the low-frequency circulating current from saturating the CIs. In this study, the zero-sequence circulating current and its alternatives are investigated using hardware and mathematical description. A high-performance circulating current controller is proposed by applying a repetitive controller to the zero-sequence current control loop. The proposed controller can effectively minimize the low-frequency circulating current without any data sharing between the inverters in unfavorable conditions. It can also be applicable to the modular configuration of parallel three-phase VSIs. Experimental results verify the performance of the proposed controller.