• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.499-503
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• 2000

The use of Multiple-Valued FFT(Fast fourier Transform) is extended from binary to multiple-valued logic(MVL) circuits. A multiple-valued FFT circuit can be implemented using current-mode CMOS techniques, reducing the transitor, wires count between devices to half compared to that of a binary implementation. For adder processing in FFT, We give the number representation using such redundant digit sets are called redundant positive-digit number representation and a Redundant set uses the carry-propagation-free addition method. As the designed Multiple-valued FFT internally using PD(positive digit) adder with the digit set 0,1,2,3 has attractive features on speed, regularity of the structure and reduced complexities of active elements and interconnections. for the mutiplier processing, we give Multiple-valued LUT(Look up table)to facilitate simple mathmatical operations on the stored digits. Finally, Multiple-valued 8point FFT operation is used as an example in this paper to illuatrates how a multiple-valued FFT can be beneficial.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.17-25
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• 2016

This paper proposes an ultra-low power design methodology for asynchronous circuits which combines with power switch structure used for reducing leakage current in the synchronous circuits. Compared to existing delay-insensitive asynchronous circuits such as static NCL and semi-static NCL, the proposed methodology provides the leakage power reduction in the NULL mode due to the high Vth of the power switches and the switching power reduction at the switching moment due to the smaller area even though it has a reasonable speed penalty. Therefore, it will become a low power design methodology required for IoT system design placing more value on power than speed. In this paper, the proposed methodology has been evaluated by a $4{\times}4$ multiplier designed using 0.11 um CMOS technology, and the simulation results have been compared to the conventional asynchronous circuits in terms of circuit delay, area, switching power and leakage power.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.