• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.71-71
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• 2012

As the critical dimensions of integrated circuits are scaled down, the line width and spacing between the metal interconnects are made smaller. The dielectric film used as insulation between the metal lines contributes to the resistance-capacitance (RC) time constant that governs the device speed. If the RC time delay, cross talk and lowering the power dissipation are to be reduced, the intermetal dielectric (IMD) films should have a low dielectric constant. The introduction of Cu and low-k dielectrics has incrementally improved the situation as compared to the conventional $Al/SiO_2$ technology by reducing both the resistivity and the capacitance between interconnects. Some of the potential candidate materials to be used as an ILD are organic and inorganic precursors such as hydrogensilsequioxane (HSQ), silsesquioxane (SSQ), methylsilsisequioxane (MSQ) and carbon doped silicon oxide (SiOCH), It has been shown that organic functional groups can dramatically decrease dielectric constant by increasing the free volume of films. Recently, various inorganic precursors have been used to prepare the SiOCH films. The k value of the material depends on the number of $CH_3$ groups built into the structure since they lower both polarity and density of the material by steric hindrance, which the replacement of Si-O bonds with Si-$CH_3$ (methyl group) bonds causes bulk porosity due to the formation of nano-sized voids within the silicon oxide matrix. In this talk, we will be introduce some properties of SiOC(-H) thin films deposited with the dimethyldimethoxysilane (DMDMS: $C_4H_{12}O_2Si$) and oxygen as precursors by using plasma-enhanced chemical vapor deposition with and without ultraviolet (UV) irradiation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권3호
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• pp.114-121
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• 2003

Through comparing stress state of TEOS and SiLK-embedded structures, the effect of low-k materials on stress and stress distribution in via-line structures were investigated using three-dimensional finite element analyses. In the case of TEOS-embedded via-line structures, hydrostatic stress was concentrated at the via and the top of the lines, where the void was suspected to nucleate. On the other hand, in the via-line structures integrated with SiLK, large von-Mises stress is maintained at the via, thus deformation of via is expected as the main failure mode. A good correlation between the calculated results and experimentally observed failure modes according to dielectric materials was obtained.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.78-78
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• 2007

In semiconductor devices, Cu has been used for the formation of multilevel metal interconnects by the damascene technique. Also lower dielectric constant materials is needed for the below 65 nm technology node. However, the low-k materials has porous structure and they can be easily damaged by high down pressure during conventional CMP. Also, Cu surface are vulnerable to have surface scratches by abrasive particles in CMP slurry. In order to overcome these technical difficulties in CMP, electro-chemical mechanical planarization (ECMP) has been introduced. ECMP uses abrasive free electrolyte, soft pad and low down-force. Especially, electrolyte is an important process factor in ECMP. The purpose of this study was to characterize KOH and $KNO_3$ based electrolytes on electro-chemical mechanical. planarization. Also, the effect of additives such as an organic acid and oxidizer on ECMP behavior was investigated. The removal rate and static etch rate were measured to evaluate the effect of electro chemical reaction.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2008년도 추계종합학술대회 B
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• pp.95-99
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• 2008

반도체 소자의 소형화에 따라 낮은 비저항을 가진 구리가 ULSI의 금속배선으로 사용되고 있다. 구리선의 비저항은 RC delay와 집적회로의 신호전달에 영향을 미치게 된다. 본 논문에서는 전기도금 된 구리박막의 비저항에 대해 전해액이 미치는 영향을 조사하였다. 4탐침 표면저항측정기로 비저항을 평가하였고, XRD (X-ray Diffraction), AFM (Atomic Force Microscope), FE-SEM (Field Emission Scanning Electron Microscope), XPS (X-ray Photoelectron Spectroscopy)로 박막의 특성을 조사하였다. 실험한 결과, 전해액의 조건이 전기도금으로 증착된 낮은 비저항을 갖는 구리박막의 형성에 있어 중요한 역할을 하는 것을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.546-546
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• 2008

Copper (Cu) Chemical mechanical polishing (CMP) has been an essential process for Cu wifing of DRAM and NAND flash memory beyond 45nm. Copper has been employed as ideal material for interconnect and metal line due to the low resistivity and high resistant to electro-migration. Damascene process is currently used in conjunction with CMP in the fabrication of multi-level copper interconnects for advanced logic and memory devices. Cu CMP involves removal of material by the combination of chemical and mechanical action. Chemicals in slurry aid in material removal by modifying the surface film while abrasion between the particles, pad, and the modified film facilitates mechanical removal. In our research, we emphasized on the role of chemical effect of slurry on Cu CMP, especially on the effect of amine functional group on removal rate selectivity between Cu and Tantalum-nitride (TaN) film. We investigated the two different kinds of complexing agent both with amine functional group. On the one hand, Polyacrylamide as a polymer affected the stability of abrasive, viscosity of slurry and the corrosion current of copper film especially at high concentration. At higher concentration, the aggregation of abrasive particles was suppressed by the steric effect of PAM, thus showed higher fraction of small particle distribution. It also showed a fluctuation behavior of the viscosity of slurry at high shear rate due to transformation of polymer chain. Also, because of forming thick passivation layer on the surface of Cu film, the diffusion of oxidant to the Cu surface was inhibited; therefore, the corrosion current with 0.7wt% PAM was smaller than that without PAM. the polishing rate of Cu film slightly increased up to 0.3wt%, then decreased with increasing of PAM concentration. On the contrary, the polishing rate of TaN film was strongly suppressed and saturated with increasing of PAM concentration at 0.3wt%. We also studied the electrostatic interaction between abrasive particle and Cu/TaN film with different PAM concentration. On the other hand, amino-methyl-propanol (AMP) as a single molecule does not affect the stability, rheological and corrosion behavior of the slurry as the polymer PAM. The polishing behavior of TaN film and selectivity with AMP appeared the similar trend to the slurry with PAM. The polishing behavior of Cu film with AMP, however, was quite different with that of PAM. We assume this difference was originated from different compactness of surface passivation layer on the Cu film under the same concentration due to the different molecular weight of PAM and AMP.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.99.1-99.1
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• 2016

The materials for an electronic packaging provide diverse important functions including electrical contact to transfer signals from devices, isolation to protect from the environment and a path for heat conduction away from the devices. The packaging materials composed of metals, ceramics, polymers or combinations are crucial to the device operating properly and reliably. The demand of effective charge and heat transfer continuous to be challenge for the high-speed and high-power devices. Nanomaterials including graphene, carbon nanotube and boron nitride, have been designed for the purpose of exploiting the high thermal, electrical and mechanical properties by combining in the matrix of metal or polymer. In addition, considering the inherent electrical and surface properties of graphene, it is expected that graphene would be a good candidate for the surface layer of a template in the electroforming process. In this talk, I will present recent our on-going works in nanomaterials for microelectronic packaging: 1) porous graphene/Cu for heat dissipations, 2) carbon-metal composites for interconnects and 3) nanomaterials-epoxy composites as a thermal interface materials for electronic packaging.

• 마이크로전자및패키징학회지
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• 제31권2호
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• pp.36-44
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• 2024

구리 전해 도금 기술은 반도체 패키징 및 반도체, 이차 전지 등 다양한 마이크로 전자 산업 분야에서 구리 박막 또는 배선의 제조를 위해 사용되고 있으며, 각 응용처에서 요구하는 특성을 획득하기 위해 이들 구리 박막 또는 배선의 미세조직을 제어하고자 광범위한 연구가 이루어지고 있다. 본 연구에서는 기계적 물성이 우수한 이차 전지용 구리 박막을 제조하기 위해, 이차 전지 제조 공정 중 기계적 또는 열적 하중에 의한 박막의 소성 변형 시 박막을 구성하는 결정립들의 결정학적 이방성의 영향성을 조사하였다. 이를 위해, 상이한 집합조직이 발달한 2 종류의 10 ㎛ 두께 전해 도금 구리 박막에 대해 전자 후방 산란 (electron backscattering diffraction or EBSD) 기술을 이용하여 표면 또는 단면의 결정 방위 지도를 측정하였고, 이들을 초기 입력 정보로 한 결정소성 유한요소해석을 통해 1축 인장 변형에 따른 박막 내부의 국부적 변형 거동을 분석하였다. 이를 통해, 인장 변형률의 증가에 따른 박막 내 소성 변형 불균질성과 집합조직의 변화를 추적하였고, 불균질한 소성 변형을 일으키는 결정립의 결정 방위를 확인하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• 한국진공학회지
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• 제20권2호
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• pp.155-163
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• 2011

탄소나노튜브(CNT)와 합성기판 사이의 전도성 향상을 목적으로, 현재 리튬이온이차전지 등의 분야에서 전극으로 이용되고 있는 구리 호일을 합성기판으로 하여, 그 위에 수직배향 CNT 성장의 합성 최적화를 도모하였다. 합성은 수평식 CVD 합성장비를 이용하였으며, 최적의 합성조건은 구리호일 위에 10 nm의 Al2O3 버퍼층과 1 nm 두께의 Fe 촉매층을 증착한 후, 아세틸렌 가스를 이용하여 $800^{\circ}C$에서 20분간 합성한 조건으로 설정하였다. CNT는 base-growth의 성장형태를 따랐고, Fe 1 nm 두께인 경우, $7.2{\pm}1.5nm$의 촉매나노입자가 형성되었으며, 이를 이용하여 $800^{\circ}C$에서 20분 성장결과, 직경 8.2 nm, 길이 $325{\mu}m$의 수직배향 CNT를 얻을 수 있었다. 합성시간이 길어져도 CNT의 결정성, 직경 및 겹(wall) 수에는 큰 변화가 없었다. 끝으로, 구리호일 위에 수직 성장시킨 CNT의 전계방출 특성을 측정한 결과, 실리콘 산화막 위에 성장시킨 CNT와 비교하여, 월등히 낮은 전계방출 문턱전압과 10배 정도 높은 전계향상계수를 보였다. 이는 CNT와 금속기판 사이의 계면에서 전기전도도가 향상된 결과에 기인하는 것으로 사료된다.

• Korean Chemical Engineering Research
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• 제45권5호
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• pp.466-472
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• 2007

웨이퍼 레벨(WL) 3차원(3D) 집적을 구현하기 위해 저유전체 고분자를 본딩 접착제로 이용한 웨이퍼 본딩과, 적층된 웨이퍼간 전기배선 형성을 위해 구리 다마신(damascene) 공정을 사용하는 방법을 소개한다. 이러한 방법을 이용하여 웨이퍼 레벨 3차원 칩의 특성 평가를 위해 적층된 웨이퍼간 3차원 비아(via) 고리 구조를 제작하고, 그 구조의 기계적, 전기적 특성을 연속적으로 연결된 서로 다른 크기의 비아를 통해 평가하였다. 또한, 웨이퍼간 적층을 위해 필수적인 저유전체 고분자 수지를 이용한 웨이퍼 본딩 공정의 다음과 같은 특성 평가를 수행하였다. (1) 광학 검사에 의한 본딩된 영역의 정도 평가, (2) 면도날(razor blade) 시험에 의한 본딩된 웨이퍼들의 정성적인 본딩 결합력 평가, (3) 4-점 굽힘시험(four point bending test)에 의한 본딩된 웨이퍼들의 정량적인 본딩 결합력 평가. 본 연구를 위해 4가지의 서로 다른 저유전체 고분자인 benzocyclobutene(BCB), Flare, methylsilsesquioxane(MSSQ) 그리고 parylene-N을 선정하여 웨이퍼 본딩용 수지에 대한 적합성을 검토하였고, 상기 평가 과정을 거쳐 BCB와 Flare를 1차적인 본딩용 수지로 선정하였다. 한편 BCB와 Flare를 비교해 본 결과, Flare를 이용하여 본딩된 웨이퍼들이 BCB를 이용하여 본딩된 웨이퍼보다 더 높은 본딩 결합력을 보여주지만, BCB를 이용해 본딩된 웨이퍼들은 여전히 칩 back-end-of-the-line (BEOL) 공정조건에 부합되는 본딩 결합력을 가지는 동시에 동공이 거의 없는 100%에 가까운 본딩 영역을 재현성있게 보여주기 때문에 본 연구에서는 BCB가 본딩용 수지로 더 적합하다고 판단하였다.