• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.111-115
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• 2014

Effect of dynamic electric fields on dielectric breakdown behavior in Cu damascene interconnects was investigated. Among the DC, unipolar, and bipolar pulse conditions, the longest dielectric lifetime is observed under the bipolar condition because backward Cu ion drift occurs when the direction of electric field is changed by 180 degrees and Cu contamination is prohibited as a results. Under the unipolar pulse condition, the dielectric lifetime increases as pulse frequency increases and it exceed the lifetime under DC condition. It suggests that the intrinsic breakdown of dielectrics significantly affect the dielectric breakdown in addition to Cu contamination. As the unipolar pulse width decreases, dielectric bond breakdown is more difficult to occur.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.123-124
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• 2005

We investigated the effect of a Ta/TaN Cu diffusion barrier existence on the reliability and the electrical performance of Cu dual-damascene interconnects. A high EM performance in Cu dual-damascene structure was observed the BCV(barrier contact via) interconnect structure to remain Ta/TaN barrier layer. Via resistance was decreased DCV interconnect structure by bottomless process. This structure considers that DCV interconnect structure has lower activation energy and higher current density than BCV interconnect structure. The EM failures by BCV via structure were formed at via hole, but DCV via structure was formed EM fail at the D2 line. In order to improve the EM characteristic of DCV interconnect structure by bottomless process, after Ta/TaN diffusion barrier layer in via bottom is removed by Ar+ resputtering process, it is desirable that Ta thickness is thickly made by Ta flash process.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.12
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• pp.37-42
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• 1999

In this paper, some of main processes for the next generation integrated circuits, such as Cu damascene process using CMP, electron beam lithography, $SiO_2$ CVD and RIE, Ti/Cu-CVD were carried cut and then, two level Cu interconnects were accomplished. In the results of CMP unit processes, a 4,635 ${\AA}$/min of removal rate, a selectivity of Cu : $SiO_2$ of 150:1, a uniformity of 4.0% are obtained under process conditions of a head pressure of 4 PSI, table and head speed of 25rpm, a oscillation distance of 40 mm, and a slurry flow rate of 40 ml/min. Also 0.18 ${\mu}m\;SiO_2$ via-line patterns are fabricated using 1000 ${\mu}C/cm^2$ dose, 6 minute and 30 second development time and 1 minute and 30 second etching time. And finally sub-0.2 ${\mu}$ twolevel metal interconnects using the developed processes were fabricated and the problems of multilevel interconnects are discussed.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.7-12
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• 2002

반도체 공정에서 구리(Cu) 배선의 미세구조와 신뢰성에 대해 연구하였는데, 특히 CVD Cu와 전기도금 Cu를 사용하여 신뢰성에 대한 texture와 결정 구조의 영향을 연구하였다 CVD Cu의 경우 여러 가지 시드층(seed layer)을 사용함으로서, 결정입자의 크기는 비슷하지만 texture가 전혀 다른 Cu 박막을 얻을 수 있었는데, 신뢰성 검사결과 (111) texture를 가진 Cu 배선의 수명이 (200) texture를 가진 Cu 배선의 수명보다 약 4배 가량 길게 나왔다. 전기도금 Cu 박막의 경우 항상 (111) texture를 갖고 있었으며 결정립의 크기도 CVD Cu의 것보다 더 컸다. Damascene 공법으로 회로 형성한 Cu 배선의 경우에도 전기도금 Cu의 결정립 크기가 CVD Cu의 것보다 더 크게 나타났으며, 신뢰성 검사결과 배선의 수명도 더 길게 나타났는데 그 차이는 0.4 $\mu\textrm{m}$ 이하의 미세선폭 영역에서 더욱 현저했다. 따라서 전기도금 Cu가 CVD Cu보다 신뢰성 측면에서 더 우수한 것으로 판명되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.114-121
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• 2003

Through comparing stress state of TEOS and SiLK-embedded structures, the effect of low-k materials on stress and stress distribution in via-line structures were investigated using three-dimensional finite element analyses. In the case of TEOS-embedded via-line structures, hydrostatic stress was concentrated at the via and the top of the lines, where the void was suspected to nucleate. On the other hand, in the via-line structures integrated with SiLK, large von-Mises stress is maintained at the via, thus deformation of via is expected as the main failure mode. A good correlation between the calculated results and experimentally observed failure modes according to dielectric materials was obtained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.528-528
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• 2007

Cu CMP widely has been using for the formation of multilevel metal interconnects by the Cu damascene process. And lower dielectric constant materials are required for the below 45nm technology node. As the dielectric constant of dielectric materials are smaller, the strength of dielectric materials become weaker. Therefore these materials are easily damaged by high down pressure during conventional CMP. Also, technical problems such as surface scratches, delamination, dishing and erosion are also occurred. In order to overcome these problems in CMP, the ECMP (electro-chemical mechanical planarization) has been introduced. In this process, abrasive free electrolyte, soft pad and low down force were used. The electrolyte is one of important factor to solve these problems. Also, additives are required to improve the removal rate, uniformity, surface roughness, defects, and so on. In this study, KOH and $NaNO_3$ based electrolytes were used for Cu ECMP and the electrochemical behavior was evaluated by the potentiostat. Also, the Cu surface was observed by SEM as a function of applied voltage and chemical concentration.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.78-78
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• 2007

In semiconductor devices, Cu has been used for the formation of multilevel metal interconnects by the damascene technique. Also lower dielectric constant materials is needed for the below 65 nm technology node. However, the low-k materials has porous structure and they can be easily damaged by high down pressure during conventional CMP. Also, Cu surface are vulnerable to have surface scratches by abrasive particles in CMP slurry. In order to overcome these technical difficulties in CMP, electro-chemical mechanical planarization (ECMP) has been introduced. ECMP uses abrasive free electrolyte, soft pad and low down-force. Especially, electrolyte is an important process factor in ECMP. The purpose of this study was to characterize KOH and $KNO_3$ based electrolytes on electro-chemical mechanical. planarization. Also, the effect of additives such as an organic acid and oxidizer on ECMP behavior was investigated. The removal rate and static etch rate were measured to evaluate the effect of electro chemical reaction.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.239-240
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• 2008

As semiconductor devices are scaled down for better performance and more functionality, the Cu-based interconnects suffer from the increase of the resistivity of the Cu wires. The resistivity increase, which is attributed to the electron scattering from grain boundaries and interfaces, needs to be addressed in order to further scale down semiconductor devices [1]. The increase in the resistivity of the interconnect can be alleviated by increasing the grain size of electroplating (EP)-Cu or by modifying the Cu surface [1]. Another possible solution is to maximize the portion of the EP-Cu volume in the vias or damascene structures with the conformal diffusion barrier and seed layer by optimizing their deposition processes during Cu interconnect fabrication, which are currently ionized physical vapor deposition (IPVD)-based Ta/TaN bilayer and IPVD-Cu, respectively. The use of in-situ etching, during IPVD of the barrier or the seed layer, has been effective in enlarging the trench volume where the Cu is filled, resulting in improved reliability and performance of the Cu-based interconnect. However, the application of IPVD technology is expected to be limited eventually because of poor sidewall step coverage and the narrow top part of the damascene structures. Recently, Ru has been suggested as a diffusion barrier that is compatible with the direct plating of Cu [2-3]. A single-layer diffusion barrier for the direct plating of Cu is desirable to optimize the resistance of the Cu interconnects because it eliminates the Cu-seed layer. However, previous studies have shown that the Ru by itself is not a suitable diffusion barrier for Cu metallization [4-6]. Thus, the diffusion barrier performance of the Ru film should be improved in order for it to be successfully incorporated as a seed layer/barrier layer for the direct plating of Cu. The improvement of its barrier performance, by modifying the Ru microstructure from columnar to amorphous (by incorporating the N into Ru during PVD), has been previously reported [7]. Another approach for improving the barrier performance of the Ru film is to use Ru as a just seed layer and combine it with superior materials to function as a diffusion barrier against the Cu. A RulTaN bilayer prepared by PVD has recently been suggested as a seed layer/diffusion barrier for Cu. This bilayer was stable between the Cu and Si after annealing at $700^{\circ}C$ for I min [8]. Although these reports dealt with the possible applications of Ru for Cu metallization, cases where the Ru film was prepared by atomic layer deposition (ALD) have not been identified. These are important because of ALD's excellent conformality. In this study, a bilayer diffusion barrier of Ru/TaCN prepared by ALD was investigated. As the addition of the third element into the transition metal nitride disrupts the crystal lattice and leads to the formation of a stable ternary amorphous material, as indicated by Nicolet [9], ALD-TaCN is expected to improve the diffusion barrier performance of the ALD-Ru against Cu. Ru was deposited by a sequential supply of bis(ethylcyclopentadienyl)ruthenium [Ru$(EtCp)_2$] and $NH_3$plasma and TaCN by a sequential supply of $(NEt_2)_3Ta=Nbu^t$ (tert-butylimido-trisdiethylamido-tantalum, TBTDET) and $H_2$ plasma. Sheet resistance measurements, X-ray diffractometry (XRD), and Auger electron spectroscopy (AES) analysis showed that the bilayer diffusion barriers of ALD-Ru (12 nm)/ALD-TaCN (2 nm) and ALD-Ru (4nm)/ALD-TaCN (2 nm) prevented the Cu diffusion up to annealing temperatures of 600 and $550^{\circ}C$ for 30 min, respectively. This is found to be due to the excellent diffusion barrier performance of the ALD-TaCN film against the Cu, due to it having an amorphous structure. A 5-nm-thick ALD-TaCN film was even stable up to annealing at $650^{\circ}C$ between Cu and Si. Transmission electron microscopy (TEM) investigation combined with energy dispersive spectroscopy (EDS) analysis revealed that the ALD-Ru/ALD-TaCN diffusion barrier failed by the Cu diffusion through the bilayer into the Si substrate. This is due to the ALD-TaCN interlayer preventing the interfacial reaction between the Ru and Si.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.546-546
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• 2008

Copper (Cu) Chemical mechanical polishing (CMP) has been an essential process for Cu wifing of DRAM and NAND flash memory beyond 45nm. Copper has been employed as ideal material for interconnect and metal line due to the low resistivity and high resistant to electro-migration. Damascene process is currently used in conjunction with CMP in the fabrication of multi-level copper interconnects for advanced logic and memory devices. Cu CMP involves removal of material by the combination of chemical and mechanical action. Chemicals in slurry aid in material removal by modifying the surface film while abrasion between the particles, pad, and the modified film facilitates mechanical removal. In our research, we emphasized on the role of chemical effect of slurry on Cu CMP, especially on the effect of amine functional group on removal rate selectivity between Cu and Tantalum-nitride (TaN) film. We investigated the two different kinds of complexing agent both with amine functional group. On the one hand, Polyacrylamide as a polymer affected the stability of abrasive, viscosity of slurry and the corrosion current of copper film especially at high concentration. At higher concentration, the aggregation of abrasive particles was suppressed by the steric effect of PAM, thus showed higher fraction of small particle distribution. It also showed a fluctuation behavior of the viscosity of slurry at high shear rate due to transformation of polymer chain. Also, because of forming thick passivation layer on the surface of Cu film, the diffusion of oxidant to the Cu surface was inhibited; therefore, the corrosion current with 0.7wt% PAM was smaller than that without PAM. the polishing rate of Cu film slightly increased up to 0.3wt%, then decreased with increasing of PAM concentration. On the contrary, the polishing rate of TaN film was strongly suppressed and saturated with increasing of PAM concentration at 0.3wt%. We also studied the electrostatic interaction between abrasive particle and Cu/TaN film with different PAM concentration. On the other hand, amino-methyl-propanol (AMP) as a single molecule does not affect the stability, rheological and corrosion behavior of the slurry as the polymer PAM. The polishing behavior of TaN film and selectivity with AMP appeared the similar trend to the slurry with PAM. The polishing behavior of Cu film with AMP, however, was quite different with that of PAM. We assume this difference was originated from different compactness of surface passivation layer on the Cu film under the same concentration due to the different molecular weight of PAM and AMP.

• Korean Chemical Engineering Research
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• v.45 no.5
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• pp.466-472
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• 2007

A technology platform for wafer-level three-dimensional integration circuits (3D-ICs) is presented, and that uses wafer bonding with low-k polymeric adhesives and Cu damascene inter-wafer interconnects. In this work, one of such technical platforms is explained and characterized using a test vehicle of inter-wafer 3D via-chain structures. Electrical and mechanical characterizations of the structure are performed using continuously connected 3D via-chains. Evaluation results of the wafer bonding, which is a necessary process for stacking the wafers and uses low-k dielectrics as polymeric adhesive, are also presented through the wafer bonding between a glass wafer and a silicon wafer. After wafer bonding, three evaluations are conducted; (1) the fraction of bonded area is measured through the optical inspection, (2) the qualitative bond strength test to inspect the separation of the bonded wafers is taken by a razor blade, and (3) the quantitative bond strength is measured by a four point bending. To date, benzocyclobutene (BCB), $Flare^{TM}$, methylsilsesquioxane (MSSQ) and parylene-N were considered as bonding adhesives. Of the candidates, BCB and $Flare^{TM}$ were determined as adhesives after screening tests. By comparing BCB and $Flare^{TM}$, it was deduced that BCB is better as a baseline adhesive. It was because although wafer pairs bonded using $Flare^{TM}$ has a higher bond strength than those using BCB, wafer pairs bonded using BCB is still higher than that at the interface between Cu and porous low-k interlevel dielectrics (ILD), indicating almost 100% of bonded area routinely.