• Journal of Advanced Information Technology and Convergence
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• v.9 no.2
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• pp.115-123
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• 2019

White-box cryptography is an implementation technique in order to protect secret keys of cryptographic algorithms in the white-box attack model, which is the setting that an adversary has full access to the implementation of the cryptographic algorithm and full control over their execution. This concept was introduced in 2002 by Chow et al., and since then, there have been many proposals for secure implementations. While there have been many approaches to construct a secure white-box implementation for the ciphers with SPN structures, there was no notable result about the white-box implementation for the block ciphers with Feistel structure after white-box DES implementation was broken. In this paper, we propose a secure white-box implementation for a block cipher SEED with Feistel structure, which can prevent the previous known attacks for white-box implementations. Our proposal is simple and practical: it is performed by only 3,376 table lookups during each execution and the total size of tables is 762.5 KB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.9B
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• pp.1609-1617
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• 2000

In this paper a design of cryptographic coprocessor which implements SEED algorithm is described. To satisfy trade-off between area and speed, the coprocessor has structure in which 1 round operation is divided into three subrounds and then subround is executed for one clock. To improve clock frequency online precomputation scheme for round key is used. To apply the coprocessor to various applications, four operating modes such as ECB, CBC, CFB, and OFB are supported. Also to eliminate performance degradation due to data input and data output time between host computer and coprocesor, background input/output method is used. The cryptographic coprocessor is designed using $0.25{\mu}{\textrm}{m}$ CMOS technology and consists of about 29,300 gates. Its peak performance is about 237 Mbps encryption or decryption rate under 100 Mhz clock frequncy and ECB mode.

• International Journal of Computer Science & Network Security
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• v.21 no.11
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• pp.354-362
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• 2021

The device to device (D2D) communication is an important and emerging area for future cellular networks. It is concerned about all aspect of secure data transmission between end devices along with originality of the data. In this paradigm, the major concerns are about how keys are delivered between the devices when the devices require the cryptographic keys. Another major concern is how effectively the receiver device verifies the data sent by the sender device which means that the receiver checks the originality of the data. In order to fulfill these requirements, the proposed system able to derive a cryptographic key using a single secret key and these derived keys are securely transmitted to the intended receiver with procedure called mutual authentication. Initially, derived keys are computed by applying robust procedure so that any adversary feel difficulties for cracking the keys. The experimental results shows that both sender and receiver can identify themselves and receiver device will decrypt the data only after verifying the originality of the data. Only the devices which are mutually authenticated each other can interchange the data so that entry of the intruder node at any stage is not possible.

• International Journal of Computer Science & Network Security
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• v.22 no.9
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• pp.414-426
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• 2022

Elliptic Curve Cryptography (ECC) is one of the finest cryptographic technique of recent time due to its lower key length and satisfactory performance with different hardware structures. In this paper, a High Throughput Multiplier architecture is introduced for Elliptic Cryptographic applications based on concurrent computations. With the aid of the concurrent computing approach, the High Throughput Concurrent Computation (HTCC) technology that was just presented improves the processing speed as well as the overall efficiency of the point-multiplier architecture. Here, first and second distinct group operation of point multiplier are combined together and synthesised concurrently. The synthesis of proposed HTCC technique is performed in Xilinx Virtex - 5 and Xilinx Virtex - 7 of Field-programmable gate array (FPGA) family. In terms of slices, flip flops, time delay, maximum frequency, and efficiency, the advantages of the proposed HTCC point multiplier architecture are outlined, and a comparison of these advantages with those of existing state-of-the-art point multiplier approaches is provided over GF(2¹⁶³), GF(2²³³) and GF(2²⁸³). The efficiency using proposed HTCC technique is enhanced by 30.22% and 75.31% for Xilinx Virtex-5 and by 25.13% and 47.75% for Xilinx Virtex-7 in comparison according to the LC design as well as the LL design, in their respective fashions. The experimental results for Virtex - 5 and Virtex - 7 over GF(2²³³) and GF(2²⁸³)are also very satisfactory.

• Journal of Advanced Navigation Technology
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• v.28 no.1
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• pp.142-148
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• 2024

It is difficult to apply authentication methods of existing wired or wireless networks to Internet of Things (IoT) devices due to their poor environment, low capacity, and low-performance processor. In particular, there are many problems in applying methods such as blockchain to the IoT environment. In this paper, edge computing is used to serve as a server that authenticates disposable templates among biometric information in an IoT environment. In this environment, we propose a lightweight and strong authentication procedure using the IoT-edge computing (IoT-EC) system based on elliptic curve cryptographic (ECC) and evaluate its safety.

• Journal of Convergence for Information Technology
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• v.9 no.1
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• pp.86-91
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• 2019

Block chains began by recognizing the danger of centralized control of financial systems after the 2008 financial crisis. From the beginning of 2008, blockchain has been developing a lot of attention and technology, starting with a tremendous innovation called cryptographic destruction based on technology, a block chain called Bitcoin. However, the vulnerability has also been discovered over time and the damage has been repeated. But in the fourth industry of the 21st century, many advances and technologies based on them are expected to emerge. Therefore, this paper proposes new analytical transaction protocols for vulnerabilities in cryptographic currency transactions. The proposed transaction protocol is a way to authenticate once again at the end of the transaction and the transaction is concluded with this authentication. It presents countermeasures by adding security elements between users to the transaction process rather than internal security to transaction vulnerabilities.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.778-784
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• 2012

A symmetric block cryptosystem uses an identical cryptographic key at encryption and decryption processes. HIGHT cipher algorithm is 64-bit block cryptographic technology for mobile device that was authorized as international standard by ISO/IEC on 2010. In this paper, block cipher HIGHT algorithm is designed using Verilog-HDL. Four modes of operation for block cipher such as ECB, CBC, OFB and CTR are supported. When continuous message blocks of fixed size are encrypted or decrypted, the desigend HIGHT core can process a 64-bit message block in every 34-clock cycle. The cryptographic processor designed in this paper operates at 144MHz on vertex chip of Xilinx, Inc. and the maximum throughput is 271Mbps. The designed cryptographic processor is applicable to security module of the areas such as PDA, smart card, internet banking and satellite broadcasting.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.3
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• pp.113-123
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• 2007

This paper presents a high-performance elliptic curve cryptographic processor over $GF(2^m)$. The proposed design adopts Lopez-Dahab Montgomery algorithm for elliptic curve point multiplication and uses Gaussian normal basis for $GF(2^m)$ field arithmetic operations. We select m=163 which is the smallest value among five recommended $GF(2^m)$ field sizes by NIST and it is Gaussian normal basis of type 4. The proposed elliptic curve cryptographic processor consists of host interface, data memory, instruction memory, and control. We implement the proposed design using Xilinx XCV2000E FPGA device. Based on the FPGA implementation results, we can see that our design is 2.6 times faster and requires significantly less hardware resources compared with the previously proposed best hardware implementation.

• International Journal of Computer Science & Network Security
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• v.22 no.5
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• pp.342-347
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• 2022

On Cloud, the important data of the user that is protected on remote servers can be accessed via internet. Due to rapid shift in technology nowadays, there is a swift increase in the confidential and pivotal data. This comes up with the requirement of data security of the user's data. Data is of different type and each need discrete degree of conservation. The idea of data security data science permits building the computing procedure more applicable and bright as compared to conventional ones in the estate of data security. Our focus with this paper is to enhance the safety of data on the cloud and also to obliterate the problems associated with the data security. In our suggested plan, some basic solutions of security like cryptographic techniques and authentication are allotted in cloud computing world. This paper put your heads together about how machine learning techniques is used in data security in both offensive and defensive ventures, including analysis on cyber-attacks focused at machine learning techniques. The machine learning technique is based on the Supervised, UnSupervised, Semi-Supervised and Reinforcement Learning. Although numerous research has been done on this topic but in reference with the future scope a lot more investigation is required to be carried out in this field to determine how the data can be secured more firmly on cloud in respect with the Machine Learning Techniques and cryptographic methods.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.6
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• pp.989-1000
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• 2023

In order to respond to supply chain threats, active research and development efforts are underway for software tamper prevention technologies such as Secure Boot and management systems like Software Bill of Materials(SBOM). Particularly, the Trusted Computing Group (TCG) is introducing standards for Trusted Platform Module(TPM) to provide a secure and trustworthy computing boot environment. This paper emphasizes the need for introducing secure booting technology for cryptographic modules to ensure that they remain safe and provide reliable functionality even in the face of supply chain threats. Furthermore, it analyzes vulnerabilities in cryptographic modules verified by the ISO/IEC 19790 standard and proposes security requirements for secure booting of cryptographic modules to address these vulnerabilities.