• Title/Summary/Keyword: Counter-memory

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A Study on Countermeasures for Personal Data Breach and Security Threats of Social Network Game (소셜 네트워크 게임(SNG) 서비스의 개인정보 유출 및 보안위협 대응방안에 관한 연구)

  • Lee, Sang Won;Kim, Huy Kang;Kim, Eun Jin
    • Journal of Korea Game Society
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    • v.15 no.1
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    • pp.77-88
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    • 2015
  • As the smart phone market is drastically expanding, there is a steady growth of recent vicious activities such as data manipulation, billing fraud, identity theft, and leakage of personal information that are security threats to Social Network Games(SNG). Due to the threats, Strong development standard is required for security enhancement of SNG. Nonetheless, short life-spans, additional expenses, and the necessities to provide a sound game service hinders developers from reaching their security goals. Therefore, this research investigates the weak points of SNG through memory manipulation experiments based on the currently provided SNG services. In addition, the research presents counter measures and security enforcements that are light in service load and simplistic which can be applied in the developing process.

Programmable Ministep Drive

  • Thedmolee, Sunhapitch;Pongswatd, Sawai;Kummool, Sart;Ukakimapurn, Prapart
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.2274-2277
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    • 2003
  • A cylindrical permanent magnet inside the four-phase permanent magnet (PM) stepping motor is employed as the rotor. The stator has four teeth around, which its coils are wound. The mode of excitation can be classified into 3 modes: single-phase excitation, two-phase excitation and ministep excitation. The ministep drive is a method to subdivide one step into several small steps by means of electronics. The paper presents the programmable ministep technique drive. This technique decodes the results obtained from the counter to locate the data in Read Only Memory (ROM). The Sinusoidal Pulse Width Modulation (SPWM) is transformed to binary file and saved to the ROM. The experiment is performed with the four-phase PM stepping motor and drives from a two-phase programmable sinusoidal ministep signal, instead of square wave. The results show that the performances of the proposed programmable ministep technique drive have high efficiency, smooth step motion, and high speed response. Moreover, the resolution of sinusoidal ministep signal can be controlled by the input frequency (f command).

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A study on the architecture and logic block design of FPGA (FPGA 구조 및 로직 블록의 설계에 관한 연구)

  • 윤여환;문중석;문병모;안성근;정덕균
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.11
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    • pp.140-151
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    • 1996
  • In this study, we designed the routing structure and logic block of a SRAM cell-based FPGA with symmetrical-array architecture. The designed routing structure is composed of switch matrices, routing channels and I/O blocks, and the routing channels can be subdivided into single length channels, double length channels and global length channels. The interconnection between wires is made through SRAM cell-controlled pass transistors. To reduce the signal delay in pass transistors, we proposed a scheme raising the gate-control voltage to 7V. The designed SRAM cells have built-in shift register capability, so there is no need for separate shift registers. We designed SRAM cells in the LUTs(look-up tables) to enable the wirte operations to be performed synchronously with the clock for ease of system application. Each logic block (LFU) has four 4-input LUTs, flip-flops and other gates, and the LUTs can be used a sSRAM memory. The LFU also has a dedicated carry logic, so a 4-bit adder can be implemented in one LFU. We designed our FPGA using 0.6.mu.m CMOS technology, and simulation shows proper operation of a 4 bit counter at 100MHz.

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AndroScope: An Insightful Performance Analyzer for All Software Layers of the Android-Based Systems

  • Cho, Myeongjin;Lee, Ho Jin;Kim, Minseong;Kim, Seon Wook
    • ETRI Journal
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    • v.35 no.2
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    • pp.259-269
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    • 2013
  • Android has become the most popular platform for mobile devices. However, Android still has critical performance issues, such as "application not responding" errors and hiccups resulting from garbage collection. Many phone vendors have tried to resolve the problems by characterizing and improving the performance. However, there are few insightful performance analysis tools for the Android-based systems. This paper presents AndroScope, which is a performance analysis tool for both the Android platform (Dalvik virtual machine, core libraries, Android libraries, and even Linux kernels) and its applications. To the best of our knowledge, this is the first tool to collect and analyze performance data from all the software layers of the Android-based systems. AndroScope offers a trace mechanism to collect such deep and wide performance data as hardware performance counters, time, and memory usage. In addition, the tool includes TraceBridge, which is a middleware for the fast handling of mass logs. Moreover, AndroScope offers an integrated graphical user interface with the Android software development kit to display a great volume of the detailed performance data.

Development of plane Motion Accuracy Measurement Unit of NC Lathe (NC 선반의 정면 운동정도 측정장치의 개발)

  • 김영석;한지희;정정표;윤원주;송인석
    • Journal of the Korean Society for Precision Engineering
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    • v.21 no.7
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    • pp.101-106
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    • 2004
  • Measurements of linear motion accuracy for one axis of NC lathe have achieved with laser interferometer system, but measurement of plane motion accuracy for two axes on zx-plane of NC lathe have not achieved with the above system. Therefore in this study, measuring unit system is organized using two optical linear scales in order to acquire error. data during of plane motion of ATC(Automatic Tool Change.) of NC lathe by reading zx-plane coordinates. Two optical linear scales of measuring unit are fixed on zx-plane of NC lathe, and moving part of the scales are fixed to the ATC and then error motion data of z, x-coordinates of the ATC are received from the scales through the PC counter card inserted in computer at constant time intervals using tick pulses coming out from computer. And then, error motion data files acquired from measuring are saved in computer memory and the aspect of plane motion are modeled to plots, and range of the error data, means. average deviations, and standard deviations etc. are calculated by means of statistical treatments using computer programs.

Understanding the Mismatch between ERP and Organizational Information Needs and Its Responses: A Study based on Organizational Memory Theory (조직의 정보 니즈와 ERP 기능과의 불일치 및 그 대응책에 대한 이해: 조직 메모리 이론을 바탕으로)

  • Jeong, Seung-Ryul;Bae, Uk-Ho
    • Asia pacific journal of information systems
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    • v.22 no.2
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    • pp.21-38
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    • 2012
  • Until recently, successful implementation of ERP systems has been a popular topic among ERP researchers, who have attempted to identify its various contributing factors. None of these efforts, however, explicitly recognize the need to identify disparities that can exist between organizational information requirements and ERP systems. Since ERP systems are in fact "packages" -that is, software programs developed by independent software vendors for sale to organizations that use them-they are designed to meet the general needs of numerous organizations, rather than the unique needs of a particular organization, as is the case with custom-developed software. By adopting standard packages, organizations can substantially reduce many of the potential implementation risks commonly associated with custom-developed software. However, it is also true that the nature of the package itself could be a risk factor as the features and functions of the ERP systems may not completely comply with a particular organization's informational requirements. In this study, based on the organizational memory mismatch perspective that was derived from organizational memory theory and cognitive dissonance theory, we define the nature of disparities, which we call "mismatches," and propose that the mismatch between organizational information requirements and ERP systems is one of the primary determinants in the successful implementation of ERP systems. Furthermore, we suggest that customization efforts as a coping strategy for mismatches can play a significant role in increasing the possibilities of success. In order to examine the contention we propose in this study, we employed a survey-based field study of ERP project team members, resulting in a total of 77 responses. The results of this study show that, as anticipated from the organizational memory mismatch perspective, the mismatch between organizational information requirements and ERP systems makes a significantly negative impact on the implementation success of ERP systems. This finding confirms our hypothesis that the more mismatch there is, the more difficult successful ERP implementation is, and thus requires more attention to be drawn to mismatch as a major failure source in ERP implementation. This study also found that as a coping strategy on mismatch, the effects of customization are significant. In other words, utilizing the appropriate customization method could lead to the implementation success of ERP systems. This is somewhat interesting because it runs counter to the argument of some literature and ERP vendors that minimized customization (or even the lack thereof) is required for successful ERP implementation. In many ERP projects, there is a tendency among ERP developers to adopt default ERP functions without any customization, adhering to the slogan of "the introduction of best practices." However, this study asserts that we cannot expect successful implementation if we don't attempt to customize ERP systems when mismatches exist. For a more detailed analysis, we identified three types of mismatches-Non-ERP, Non-Procedure, and Hybrid. Among these, only Non-ERP mismatches (a situation in which ERP systems cannot support the existing information needs that are currently fulfilled) were found to have a direct influence on the implementation of ERP systems. Neither Non-Procedure nor Hybrid mismatches were found to have significant impact in the ERP context. These findings provide meaningful insights since they could serve as the basis for discussing how the ERP implementation process should be defined and what activities should be included in the implementation process. They show that ERP developers may not want to include organizational (or business processes) changes in the implementation process, suggesting that doing so could lead to failed implementation. And in fact, this suggestion eventually turned out to be true when we found that the application of process customization led to higher possibilities of failure. From these discussions, we are convinced that Non-ERP is the only type of mismatch we need to focus on during the implementation process, implying that organizational changes must be made before, rather than during, the implementation process. Finally, this study found that among the various customization approaches, bolt-on development methods in particular seemed to have significantly positive effects. Interestingly again, this finding is not in the same line of thought as that of the vendors in the ERP industry. The vendors' recommendations are to apply as many best practices as possible, thereby resulting in the minimization of customization and utilization of bolt-on development methods. They particularly advise against changing the source code and rather recommend employing, when necessary, the method of programming additional software code using the computer language of the vendor. As previously stated, however, our study found active customization, especially bolt-on development methods, to have positive effects on ERP, and found source code changes in particular to have the most significant effects. Moreover, our study found programming additional software to be ineffective, suggesting there is much difference between ERP developers and vendors in viewpoints and strategies toward ERP customization. In summary, mismatches are inherent in the ERP implementation context and play an important role in determining its success. Considering the significance of mismatches, this study proposes a new model for successful ERP implementation, developed from the organizational memory mismatch perspective, and provides many insights by empirically confirming the model's usefulness.

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An Application-Specific and Adaptive Power Management Technique for Portable Systems (휴대장치를 위한 응용프로그램 특성에 따른 적응형 전력관리 기법)

  • Egger, Bernhard;Lee, Jae-Jin;Shin, Heon-Shik
    • Journal of KIISE:Computer Systems and Theory
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    • v.34 no.8
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    • pp.367-376
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    • 2007
  • In this paper, we introduce an application-specific and adaptive power management technique for portable systems that support dynamic voltage scaling (DVS). We exploit both the idle time of multitasking systems running soft real-time tasks as well as memory- or CPU-bound code regions. Detailed power and execution time profiles guide an adaptive power manager (APM) that is linked to the operating system. A post-pass optimizer marks candidate regions for DVS by inserting calls to the APM. At runtime, the APM monitors the CPU's performance counters to dynamically determine the affinity of the each marked region. for each region, the APM computes the optimal voltage and frequency setting in terms of energy consumption and switches the CPU to that setting during the execution of the region. Idle time is exploited by monitoring system idle time and switching to the energy-wise most economical setting without prolonging execution. We show that our method is most effective for periodic workloads such as video or audio decoding. We have implemented our method in a multitasking operating system (Microsoft Windows CE) running on an Intel XScale-processor. We achieved up to 9% of total system power savings over the standard power management policy that puts the CPU in a low Power mode during idle periods.

Low-Complexity Deeply Embedded CPU and SoC Implementation (낮은 복잡도의 Deeply Embedded 중앙처리장치 및 시스템온칩 구현)

  • Park, Chester Sungchung;Park, Sungkyung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.3
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    • pp.699-707
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    • 2016
  • This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

Documenting Artistic Acts of Resistance in History: Focusing on the Archives of the Art Workers' Coalition (미술가들의 저항 행위를 역사로 기억하기 미술노동자연합(AWC) 아카이브를 중심으로)

  • Lee, Hye-Rin
    • The Korean Journal of Archival Studies
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    • no.82
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    • pp.275-309
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    • 2024
  • This study examines artists' acts of resistance in the turbulent social climate of the 1960s and beyond, and considers the meaning of these documents in a contemporary context. It focuses on the Art Workers' Coalition, organised in 1969 by artists, writers, filmmakers and critics. Art Workers' Coalition demanded basic rights for artists in the art world and challenged war, discrimination, and injustice in society at large. Not only did they actively intervene in the structural problems of society through collective actions, protests, and statements, as seen in other acts of resistance, but they also expanded their reach through the medium of art. Studies of the Art Workers' Coalition, which can be considered as activist art of the late 1960s, have mainly chronicled their actions in the context of art history, without paying particular attention to the nature and value of the documentation produced in the process of resistance. However, the archives of Art Workers' Coalition have an informational and evidential value, which is a key value of archives, as they provide information not only about the activities of the organisation, but also about the activities of the individuals who comprised the unions, their intricate connections, and the social climate. In addition to the basic function of proving the activities of a group of artists, the archives of Art Workers' Coalition are also significant as a medium for providing information on people and events that have been marginalised in mainstream studies of artworks and artists, and for incorporating them into historical memory. Therefore, this study aims to identify the current status of Art Workers' Coalition-related archives as a medium to prove the activities of artists of the time, and to propose a different way of reading history through the contextual information of archives.

Intelligent Intrusion Detection and Prevention System using Smart Multi-instance Multi-label Learning Protocol for Tactical Mobile Adhoc Networks

  • Roopa, M.;Raja, S. Selvakumar
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.12 no.6
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    • pp.2895-2921
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    • 2018
  • Security has become one of the major concerns in mobile adhoc networks (MANETs). Data and voice communication amongst roaming battlefield entities (such as platoon of soldiers, inter-battlefield tanks and military aircrafts) served by MANETs throw several challenges. It requires complex securing strategy to address threats such as unauthorized network access, man in the middle attacks, denial of service etc., to provide highly reliable communication amongst the nodes. Intrusion Detection and Prevention System (IDPS) undoubtedly is a crucial ingredient to address these threats. IDPS in MANET is managed by Command Control Communication and Intelligence (C3I) system. It consists of networked computers in the tactical battle area that facilitates comprehensive situation awareness by the commanders for timely and optimum decision-making. Key issue in such IDPS mechanism is lack of Smart Learning Engine. We propose a novel behavioral based "Smart Multi-Instance Multi-Label Intrusion Detection and Prevention System (MIML-IDPS)" that follows a distributed and centralized architecture to support a Robust C3I System. This protocol is deployed in a virtually clustered non-uniform network topology with dynamic election of several virtual head nodes acting as a client Intrusion Detection agent connected to a centralized server IDPS located at Command and Control Center. Distributed virtual client nodes serve as the intelligent decision processing unit and centralized IDPS server act as a Smart MIML decision making unit. Simulation and experimental analysis shows the proposed protocol exhibits computational intelligence with counter attacks, efficient memory utilization, classification accuracy and decision convergence in securing C3I System in a Tactical Battlefield environment.