• Speech Sciences
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• v.6
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• pp.219-233
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• 1999

This paper presents a real-time implementation of a speaker independent speech recognition system based on a discrete hidden markov model(DHMM). This system is developed for a car navigation system to design on-chip VLSI system of speech recognition which is used by fixed point Oak DSP core of DSP GROUP LTD. We analyze recognition procedure with C language to implement fixed point real-time algorithms. Based on the analyses, we improve the algorithms which are possible to operate in real-time, and can verify the recognition result at the same time as speech ends, by processing all recognition routines within a frame. A car noise is the colored noise concentrated heavily on the low frequency segment under 400 Hz. For the noise robust processing, the high pass filtering and the liftering on the distance measure of feature vectors are applied to the recognition system. Recognition experiments on the twelve isolated command words were performed. The recognition rates of the baseline recognizer were 98.68% in a stopping situation and 80.7% in a running situation. Using the noise processing methods, the recognition rates were enhanced to 89.04% in a running situation.

• The Magazine of the IEIE
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• v.25 no.5
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• pp.31-41
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• 1998

With the advent of portable electronic systems, power consumption has recently become a major issue in circuit and system design. Furthermore, the sophisticated fabrication technology makes it possible to embed more functions and features in a VLSI chip, consequently calling for both higher performance and lower power to deal with the ever growing complexity of system algorithms than in the past. VLSI designers should cope with two conflicting constraints, high performance and low power, offering an optimum trade off of these constraints to meet requirements of system. Historically, VLSI designers have focused on performance improvement, and power dissipation was not a design criteria but an afterthought. This design paradigm should be changed, as power is emerging as the most critical design constraint. In VLSI design, low power design can be accomplished through many ways, for instance, process, circuit/logic design, architectural design, and etc.. In this paper, a few low power design examples, which have been used in 8 bit micro-controller core, and can be used also in 4/16/32 bit micro-controller cores, are presented in the areas of circuit, logic and architectural design. We first propose a low power guidelines for micro-controller design in SAMSUNG, and more detailed design examples are followed applying 4 specific design guidelines. The 1st example shows the power reduction through reduction of number of state clocks per instruction. The 2nd example realized the power reduction by applying RISC(Reduced Instruction Set Computer) concept. The 3rd example is to optimize the algorithm for ALU(Arithmetic Logic Unit) to lower the power consumption, Lastly, circuit cells designed for low power are described.

• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.8
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• pp.764-770
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• 2001

In this paper, we propose a novel PCI bus based parallel fuzzy inference system for transferring and inferencing the large volumes of fuzzy data in high speed. For this, the PCI 9050 interface chip is used to connect a local bus design as a PCI target core using FPGA to the PCI bus. We design and implement the PCI target core by using VHDL to be processed in parallel by considering the points of parallelyzing each element of the membership functions and each block of the condition and/or consequent parts. The proposed system can be used in a system requiring a rapid inference time in a real-time system or pattern recognition on the large volume of satellite images that have many inference variables in the condition and consequent parts.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.62-74
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• 2008

In this paper, we would like to propose the design of symmetric digital filter core in order to use in the radio astronomy. The function of FIR filter core would be designed by VHDL code required at the Data Acquisition System (DAS) of Korean VLBI Network (KVN) based on the FPGA chip of Vertex-4 SX55 model of Xilinx company. The designed digital filter has the symmetric structure to increase the effectiveness of system by sharing the digital filter coefficient. The SFFU(Symmetric FIR Filter Unit) use the parallel processing method to perform the data processing efficiently by using the constrained system clock. In this paper, therefore, for the effective design of SFFU, the Unified Synthesis software ISE Foundation and Core Generator which has excellent GUI environment were used to overall IP core synthesis and experiments. Through the synthesis results of digital filter core, we verified the resource usage is less than 40% such as Slice LUT and achieved the maximum operation frequency is more than 260MHz. We also confirmed the SFFU would be well operated without error according to the SFFU simulation result using the Modelsim 6.1a of Mentor Graphics Company. To verify the function of SFFU, we carried out the additional simulation experiments using the pseudo signal to the Matlab software. From the comparison experimental results of simulation and the designed digital FIR filter, we confirmed the FIR filter was well performed with filter's basic function. So we verified the effectiveness of the designed FIR digital filter with symmetric structure using FPGA and VHDL.

• Journal of the Korea Society of Computer and Information
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• v.19 no.4
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• pp.1-8
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• 2014

As cores in multi-core processors are integrated in a single chip, power density increased considerably, resulting in high temperature. For this reason, many research groups have focused on the techniques to solve thermal problems. In general, the approaches using mechanical cooling system or DTM(Dynamic Thermal Management) have been used to reduce the temperature in the microprocessors. However, existing approaches cannot solve thermal problems due to high cost and performance degradation. However, floorplan scheme does not require extra cooling cost and performance degradation. In this paper, we propose the diverse floorplan schemes in order to alleviate the thermal problem caused by the hottest unit in multi-core processors. Simulation results show that the peak temperature can be reduced efficiently when the hottest unit is located near to L2 cache. Compared to baseline floorplan, the peak temperature of core-central and core-edge are decreased by $8.04^{\circ}C$, $8.05^{\circ}C$ on average, respectively.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.700-702
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• 1998

자바(Java)의 수행 성능을 향상시키기 위한 방법으로 자바 프로세서가 제안되었다. 그러나 현재의 자바 프로세서는 자바 가상 머신(Java Virtual Macjine)의 구조만을 고려한 것이다. 본 논문에서는 기존 자바 프로세서의 성능을 향상시키는 자바 프로그래밍에서 사용되는 다중스레드를 직접 지원하는 새로운 자바 프로세서인 동시 다중스레드 자바 칩(Simultaneous Multithreaded Java Chip SMTJC)을 제안한다. SMTJC은 두 개의 독립적인 스레드를 동시에 수행함으로써, 자바 프로그램에서의 명령어 수준 병렬성(Instruction level parallelism)을 향상시킨다. 다중스레드 수행을 위해 새로운 스택 캐쉬의 구조 및 운영 방법을 사용한다. JavaSim을 통한 시뮬레이션은 SMTJC 이 기존 자바 프로세서에 비해 이중 스택 캐쉬와 추가적 처리 유닛들로 인해 1.28~2.00의 전체적 수행 성능이 향상됨을 보여준다. 본 연구는 하드웨어와 소프트웨어의 상호 보안적인 기술적 경향을 배경으로 자바의 언어적 특성을 고려한 프로세서를 설계, 지원함으로써 자바 프로세서의 성능 향상을 도모하고 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.190-197
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• 2011

This paper presents a 144 GHz divide-by-2 injection locked frequency divider (ILFD) with inductive feedback developed in a commercial 90-nm Si RFCMOS technology. It was demonstrated that division-by-2 operation is achieved with input power down to -12 dBm, with measured locking range of 0.96 GHz (144.18 - 145.14 GHz) at input power of -3 dBm. To the authors' best knowledge, this is the highest operation frequency for ILFD based on a 90-nm CMOS technology. From supply voltage of 1.8 V, the circuit draws 5.7 mA including both core and buffer. The fabricated chip occupies 0.54 mm ${\times}$ 0.69 mm including the DC and RF pads.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.70-83
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• 2001

In this paper, the recent progress of RF MEMS research for wireless/mobile communications is reviewed. The RF MEMS components reviewed in this paper include RF MEMS switches, tunable capacitors, high Q inductors, and thin film bulk acoustic resonators (TFBARs) to become core components for constructing miniaturized on chip RF transceiver with multi-band and multi-mode operation. Specific applications are also discussed for each of these components with emphasis on for miniaturization, integration, and performance enhancement of existing and future wireless transceiver developments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.6-11
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• 2011

We have developed dissolved ozone decompose system in the used ozonated water for the semiconductor and LCD fabrication processes, which will be base of obtaining core process technology in the high performance, low price semiconductor and LCD fabrications. Using this technology, it is possible for the semiconductor wafer and LCD planer to process more rapid and chip, and productivity will be improved.

• Proceedings of the KIEE Conference
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• 2008.04c
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• pp.140-142
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• 2008

Thrust ripples in Permanent Magnet Linear Motor(PMLSM) are mainly generated by cogging force. Cogging force caused by the interaction between the iron core and the Permanent Magnet(PM), and end effect. This paper has proposed a control method for thrust ripples suppression and design of one-chip proceeding digital controller using TMS320LF2407. This control method is realized by Field Oriented Control(FOC) adding to current compensation. The effectiveness of proposed control method is verified by experimentation comparing between the compensation and non-compensation.