• Journal of KIISE:Information Networking
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• v.29 no.4
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• pp.375-385
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• 2002

The IETF has defined the Intserv model and the RSVP signaling protocol to improve QoS capability for a set of newly emerging services including voice and video streams that require high transmission bandwidth and low delay. However, since the current Intserv model requires each router to maintain the states of each service flow, the complexity and the overhead for processing packets in each rioter drastically increase as the size of the network increases, giving rise to the scalability problem. This motivates our work; namely, we investigate and devise new control schemes to enhance the scalability of the Intesev model. To do this, we basically resort to the SCORE network model, extend it to fairly well adapt to the three services presented in the Intserv model, and devise schemes of the QoS scheduling, the admission control, and the edge and core node architectures. We also carry out the computer simulation by using ns-2 simulator to examine the performance of the proposed scheme in respects of the bandwidth allocation capability, the packet delay, and the packet delay variation. The results show that the proposed scheme meets the QoS requirements of the respective three services of Intserv model, thus we conclude that the proposed scheme enhances the scalability, while keeping the efficiency of the current Intserv model.

• Structural Engineering and Mechanics
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• v.85 no.2
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• pp.233-246
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• 2023

Bending and buckling analysis of multi-directional porous functionally graded sandwich plate has been performed for two cases namely: FG skin with homogeneous core and FG core with homogeneous skin. The principle of virtual displacements was employed and the solution was obtained using Navier's technique. This theory imposes traction-free boundary conditions on the surfaces and does not require shear correction factors. The validation of the present study has been performed with those available in the literature. The composition of metal-ceramic-based FGM changes in longitudinal and transverse directions according to the power law. Different porosity laws, such as uniform distribution, unevenly and logarithmically uneven distributions were used to mimic the imperfections in the functionally graded material that were introduced during the fabrication process. Several sandwich plates schemes were studied based on the plate's symmetry and the thickness of each layer. The effects of grading parameters and porosity laws on the bending and buckling of sandwich plates were examined.

• Nuclear Engineering and Technology
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• v.54 no.5
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• pp.1789-1803
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• 2022

RAST-F is a new full-core analysis code based on the two-step approach that couples a multi-group cross-section generation Monte-Carlo code MCS and a multi-group nodal diffusion solver. To demonstrate the feasibility of using MCS/RAST-F for fast reactor analysis, this paper presents the coupled nodal code verification results for the MET-1000 and CAR-3600 benchmark cores. Three different multi-group cross-section calculation schemes are employed to improve the agreement between the nodal and reference solutions. The reference solution is obtained by the MCS code using continuous-energy nuclear data. Additionally, the MCS/RAST-F nodal solution is verified with results based on cross-section generated by collision probability code TULIP. A good agreement between MCS/RAST-F and reference solution is observed with less than 120 pcm discrepancy in k_eff and less than 1.2% root-mean-square error in power distribution. This study confirms the two-step approach MCS/RAST-F as a reliable tool for the three-dimensional simulation of reactor cores with fast spectrum.

• Journal of the Korea Society of Computer and Information
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• v.20 no.6
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• pp.59-76
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• 2015

Recent wide spread of embedded devices and technology growth of broadband communication has led to rapid increase in the volume of created and managed data. As a result, data centers have to increase the storage capacity cost-effectively to store the created data. Data deduplication is one way to save the storage space by removing redundant data. This work propose IO extent based deduplication schemes called CORE-Dedup that exploits content-preserving access locality. We acquire IO traces from block device layer in virtual machine host, and compare the deduplication performance of chunking method between the fixed size and IO extent based. At multiple workload of 10 user's compile in virtual machine environment, the result shows that 4 KB fixed size chunking and IO extent based chunking use chunk index 14500 and 1700, respectively. The deduplication rate account for 60.4% and 57.6% on fixed size and IO extent chunking, respectively.

• KIISE Transactions on Computing Practices
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• v.23 no.8
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• pp.466-472
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• 2017

Hardware Transactional Memory (HTM) has greatly changed the parallel programming paradigm for transaction processing. Since Intel has recently proposed Transactional Synchronization Extension (TSX), a number of studies based on HTM have been conducted. However, the existing studies support conflict prediction for a single cause of the transaction processing and provide a standardized TSX environment for all workloads. To solve the problems, we propose an efficient hardware transactional memory scheme for processing transactions in multi-core in-memory environment. First, the proposed scheme determines whether to use Software Transactional Memory (STM) or the serial execution as a fallback path of HTM by using a prediction matrix to collect the information of previously executed transactions. Second, the proposed scheme performs efficient transaction processing according to the characteristic of a given workload by providing a retry policy based on machine learning algorithms. Finally, through the experimental performance evaluation using Stanford transactional applications for multi-processing (STAMP), the proposed scheme shows 10~20% better performance than the existing schemes.

• The Journal of the Korea Contents Association
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• v.18 no.10
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• pp.443-452
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• 2018

With the explosively increasing intellectual property rights, securing technological competitiveness of companies is more and more important. In particular, since patents include core technologies and element technologies, patent analysis researches are actively conducted to measure the technological value of companies. Various patent analysis studies have been conducted by the International Patent Classification(IPC), which does not include the latest technical classification, and the technical classification accuracy is low. In order to overcome this problem, the Cooperative Patent Classification(CPC), which includes the latest technology classification and detailed technical classification, has been developed. In this paper, we propose a model to analyze the classification of the technologies included in the patent by using the detailed classification system of CPC. It is possible to analyze the inventor's patents in consideration of the relation, importance, and efficiency between the detailed classification schemes of the CPCs to extract the core technology fields and to analyze the details more accurately than the existing IPC-based methods. Also, we perform the comparative evaluation with the existing IPC based patent analysis method and confirm that the proposed model shows better performance in analyzing the inventor's core technology classification.

• The Journal of Korean Institute of Next Generation Computing
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• v.13 no.2
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• pp.49-61
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• 2017

Transactional Memory (TM) has greatly changed the parallel programming paradigm for transaction processing and is classified into STM, HTM, HyTM according to hardware or software frameworks. However, the existing studies have a problem that they provide static retry policy for all workloads. To solve the problems, we propose an hybrid transactional memory scheme using sampling-based adaptive retry policy in multi-core environment. First, the proposed scheme determines whether to use STM or HTM according to the characteristic of a transaction. Otherwise, it executes HTM and STM concurrently by using a bloom filter. Second, the proposed scheme provides adaptive retry policy for HTM according to the characteristic of transactions in each workload. Finally, through the experimental performance evaluation using STAMP, the proposed scheme shows 10~20% better performance than the existing schemes.

• Journal of the Korea Society of Computer and Information
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• v.19 no.4
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• pp.1-8
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• 2014

As cores in multi-core processors are integrated in a single chip, power density increased considerably, resulting in high temperature. For this reason, many research groups have focused on the techniques to solve thermal problems. In general, the approaches using mechanical cooling system or DTM(Dynamic Thermal Management) have been used to reduce the temperature in the microprocessors. However, existing approaches cannot solve thermal problems due to high cost and performance degradation. However, floorplan scheme does not require extra cooling cost and performance degradation. In this paper, we propose the diverse floorplan schemes in order to alleviate the thermal problem caused by the hottest unit in multi-core processors. Simulation results show that the peak temperature can be reduced efficiently when the hottest unit is located near to L2 cache. Compared to baseline floorplan, the peak temperature of core-central and core-edge are decreased by $8.04^{\circ}C$, $8.05^{\circ}C$ on average, respectively.

• Proceedings of the Korean Society for Information Management Conference
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• 2002.08a
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• pp.27-33
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• 2002

본 연구의 목적은 웹 상의 다양한 학술정보자원들을 자료유형별로 효율적인 검색이 가능하도록 다양한 형태의 웹 학술정보자원에 대한 자료유형 분류체계 방안을 제시하는데 있다. 본 연구에서는 DCMI(DublinCore Metadata Initiative)를 비롯한 국내외 주요 기관이 연구·개발한 7개의 자료유형 요소 셋을 조사·분석하여, 이를 의미적으로 매핑시키고 그 결과를 참조하여 웹 학술정보자원의 특성에 맞게 10개의 범주 내에 37개의 자료유형 요소를 도출하였다. 본 연구에서 제시하는 자료유형 분류체계는 웹 학술정보자원에 공통적으로 포함되는 요소이므로 각 학문주제별로 적용시킬 경우에는 자료유형 요소의 추가 및 변경을 요구할 수도 있다.

• Journal of the Korean Society for Precision Engineering
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• v.28 no.9
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• pp.1011-1017
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• 2011

Servo control loops are a core part in the control architecture of machine tools. Servo control loops manage acceleration, velocity and position of all the axes in a machine tool based on commands. The performance of servo control loops sets the basis for quality of production paris and cycle time reduction. First, this paper presents a general control architecture of machine tools and several control schemes in literature, which can be applicable to machine tools control; including Zero Phase Error Tracking Control (ZPETC) and Cross Coupling Control (CCC). After that, modem control strategies to mitigate the problem of high speed machining are reviewed. In high speed machining, high accelerations excite the machine structure up to high frequencies, thereby exciting the structure's modes of vibration. These structural vibrations need to be damped if accurate positioning or trajectory following is required. Input shaping is an attractive option in dealing with structural vibrations. The advantages and drawbacks of using input shaping technique for machine tools are discussed in detail.