• Title/Summary/Keyword: Core design

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Forming Analysis of L-type Bending of Sandwich Sheet with Pyramid Core (피라미드 코어를 가진 샌드위치 판재의 L형 굽힘 성형해석)

  • Lim, Sung-Jin;Chung, Wan-Jin;Kim, Jong-Ho
    • Elastomers and Composites
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    • v.44 no.4
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    • pp.378-383
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    • 2009
  • In this study, the use of a condensed model is proposed for the simulation of forming of sandwich sheet with pyramid core. A corresponding finite element analysis for L-type bending is carried out to prove the accuracy and the effectiveness. In order to improve the accuracy of forming analysis, more precise modeling of core shape and consideration of work-hardening of previous core forming are carried out. Simulation results are compared with those of experiment. Deformation shape and post-buckling behavior by simulation are in good agreement with those of experiment for the considerable range of deformation. From the comparison of force-displacement curve, it is shown that the proposed model shows good prediction of post-buckling behavior.

The Hardware Design of Integrated Security Core for IoT Devices (사물인터넷 기기를 위한 통합 보안 코어의 하드웨어 설계)

  • Gookyi, Dennis A.N.;Ryoo, Kwangki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2017.10a
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    • pp.584-586
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    • 2017
  • In this paper we provide a unified crypto core that integrates lightweight symmetric cryptography and authentication. The crypto core implements a unified 128 bit key architecture of PRESENT encryption algorithm and a new lightweight encryption algorithm. The crypto core also consist of an authentication unit which neglects the use of hashing algorithms. Four algorithms are used for authentication which come from the Hopper-Blum (HB) and Hopper-Blum-Munilla-Penado (HB-MP) family of lightweight authentication algorithms: HB, HB+, HB-MP and HB-MP+. A unified architecture of these algorithms is implemented in this paper. The unified cryptosystem is designed using Verilog HDL, simulated with Modelsim SE and synthesized with Xilinx Design Suite 14.3. The crypto core synthesized to 1130 slices at 189Mhz frequency on Spartan6 FPGA device.

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Vibration Analysis of a Generator-Stator Core Under Electromagnetic Excitation (전자기력에 의한 발전기 고정자 코어의 진동 해석)

  • 김철홍;주영호;박종포
    • Journal of KSNVE
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    • v.9 no.4
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    • pp.747-753
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    • 1999
  • This paper presents results of vibration analysis of a generator-stator core for 500 MW fossil power plant. A finite element analysis using a commercial S/W is performed to estimate alternating electromagnetic forces, mainly of 120 Hz in 60 Hz machines, acting on the core, and then to calculate forced response of the core. Results are compared with design requirements.

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Choice technique develovement of transformer core (변압기 코아의 선정 기술 개발)

  • Lee, O.K.;Kim, S.Y.;Park, D.H.
    • Proceedings of the KIEE Conference
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    • 2003.07c
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    • pp.1604-1606
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    • 2003
  • In this paper, investigated the core of transformer of high power factor and high effectiveness about design and choice technology. Transformer that use existent general core and material is high no-load loss power. Presented core choice method that can reduce loss. Could do to reduce loss according to choice technology of use material more than about 10 (%). Presented classification and check list by Core's type.

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Process Induced Warpage Simulation for Panel Level Package (기판 소재에 따른 패널 레벨 패키지 공정 단계별 warpage 해석)

  • Moon, Ayoung;Kim, Sungdong
    • Journal of the Microelectronics and Packaging Society
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    • v.25 no.4
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    • pp.41-45
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    • 2018
  • We have simulated the process induced warpage for panel level package using finite element method. Silicon chips of $5{\times}5mm^2$ were redistributed on $122.4{\times}93.6mm^2$ size panel and the total number of redistributed chips was 221. The warpage at each process step, for example, (1) EMC molding, (2) attachment of detach core, (3) heating, (4) removal of a carrier, and (5) cooling was simulated using ANSYS and the effects of detach core and carrier materials on the warpage were investigated. The warpage behaved complexly depending on the materials for the detach core and carrier. However, glass carrier showed the lower warpage than FR4 carrier regardless of detach core material, and the minimum warpage was observed when the glass was used for the detach core and carrier at the same time.

Design of an Integrated Inductor with Magnetic Core for Micro-Converter DC-DC Application

  • Dhahri, Yassin;Ghedira, Sami;Besbes, Kamel
    • Transactions on Electrical and Electronic Materials
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    • v.17 no.6
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    • pp.369-374
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    • 2016
  • This paper presents a design procedure of an integrated inductor with a magnetic core for power converters. This procedure considerably reduces design time and effort. The proposed design procedure is verified by the development of an inductor model dedicated to the monolithic integration of DC-DC converters for portable applications. The numerical simulation based on the FEM (finite elements method) shows that 3D modeling of the integrated inductor allows better estimation of the electrical parameters of the desired inductor. The optimization of the electrical parameter values is based on the numerical analysis of the influence of the geometric parameters on the electrical characteristics of the inductor. Using the VHDL-AMS language, implementation of the integrated inductor in a micro Buck converter demonstrate that simulation results present a very promising approach for the monolithic integration of DC-DC converters.

Generation of Cavity and Core Plates of an Injection Mold for a Pseudo-Solid Part Model (의사 솔리드 모델의 캐비티 및 코어판 생성)

  • 장진우;이상헌;임성락
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2003.06a
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    • pp.1601-1604
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    • 2003
  • This paper describes a split operation for generation of core and cavity plates of an injection mold for a pseudo-solid model of a plastic part. Here, a pseudo-solid model means a sheet model that looks like a solid model. but whose boundary is not closed. When a solid model created in a different CAD system is imported through standard data exchange format, a pseudo-solid model is created in most cases as tolerance or some other problems make sewing operation failed. As most existing mold design system based on solid modeling kernels require a complete part solid model, mold designers have to do time-consuming healing operations to convert a pseudo-solid to solid. The essential capability of mold design system is the split operation for generation of core and cavity plates. Thus. we developed a split operation for pseudo-solid part model to eliminate or reduce healing preprocessing for mold design.

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An Optimal Design of Sandwich Panels with Wire-woven Bulk Kagome Cores (와이어 직조 카고메 다공질 금속을 심재로 갖는 샌드위치 판재의 최적 설계)

  • Lee, Yong-Hyun;Kang, Ki-Ju
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.32 no.9
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    • pp.782-787
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    • 2008
  • First, the effect of the geometry such as the curved shape of the struts composing the truss structure of WBK is elaborated. Then, analytic solutions for the material properties of WBK and the maximum loads of a WBK-cored sandwich panel under bending are derived. A design optimization with the face sheet thickness and the core height selected as the design variables is presented for given slenderness ratios of the WBK core. Unless the face sheet thickness is limited, the optimal design to give the maximum load per weight is always found at a confluence of three failure modes, namely, face sheet yielding, indentation plastic, and core shear modeB plastic.

A Low Power Design of H.264 Codec Based on Hardware and Software Co-design

  • Park, Seong-Mo;Lee, Suk-Ho;Shin, Kyoung-Seon;Lee, Jae-Jin;Chung, Moo-Kyoung;Lee, Jun-Young;Eum, Nak-Woong
    • Information and Communications Magazine
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    • v.25 no.12
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    • pp.10-18
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    • 2008
  • In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.