• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 춘계학술발표강연 및 논문개요집
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• pp.86-86
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• 2003

Copper has attracted much attention in the deep submicron ULSI metallization process as a replacement for aluminum due to its lower resistivity and higher electromigration resistance. Electroless copper deposition method is appealing because it yields conformal, high quality copper at relatively low cost and a low processing temperature. In this work, it was investigated that effect of the microstructure of the substrate on the electroless deposition. The mechanism of the nucleation and growth of the palladium nuclei during palladium activation was proposed. Electroless copper deposition on TiN barriers using glyoxylic acid as a reducing agent was also investigated to replace toxic formaldehyde. Furthermore, electroless copper deposition on TaN$\sub$x/ barriers was examined at various nitrogen flow rate during TaN$\sub$x/ deposition. Finally, it was investigated that the effect of plasma treatment of as-deposited TaN$\sub$x/ harriers on the electroless copper deposition.

• 한국표면공학회지
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• 제29권6호
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• pp.803-808
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• 1996

Material and electrical characteristies of copper thin films prepared by metal organic chemical vapor deposition (MOCVD) have been investigated for interconnection applications in ultra large scale integration circuits (ULSI). The copper films have been deposited a TiN substrates using a metal organic precursor, hexafluoro acetylacetonate trimethyvinylsilane copper, VTMS(hfac)Cu (I). Deposition rate, grain size, surface morphology, and electrical resistvity of the copper films have been measuredfrom samples prepared at various experimental conditions, which include substrate temperature, chamber pressure, and carrier gas flow rate. Results of the experiment showed that the electrical property of the copper films is closely related to the crystallinity of the films. Lowest electrical resistivity, $2.4{\mu}{\Omega}.cm$ was obtained at the substrate temperature of $180^{\circ}C$, but the resistivity slightly increased with increasing substrate temperature due to the carbon content along the copper grain boundaries.

• 마이크로전자및패키징학회지
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• 제9권3호
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• pp.1-6
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• 2002

A low temperature process technology of copper thin films has been developed by a chemical vapor deposition technology for multi-level metallzations in ULSI fabrication. The copper films were deposited on TiN/Si substrates in helium atmosphere with the substrate temperature between $130^{\circ}C$ and $250^{\circ}C$. In order to get more reliable metallizations, effects on the post-annealing treatment to the electrical properties of the copper films have been investigated. The Cu films were annealed at the $5 \times10^{-6}$ Torr vacuum condition and the electrical resistivity and the nano-structures were measured for the Cu films. The electrical resistivity of Cu films shown to be reduced by the post-annealing. The electrical resistivity of 2.0 $\mu \Omega \cdot \textrm{cm}$ was obtained for the sample deposited at the substrate temperature of $180^{\circ}C$ after vacuum annealed at $300^{\circ}C$. The resistivity variations of the films was not exactly matched with the size of the nano-structures of the copper grains, but more depended on the contamination of the copper films.

• 한국전기전자재료학회논문지
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• 제22권2호
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• pp.123-127
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• 2009

In order to get more higher integration density of devices, it is getting to be used more and more micro via interconnection lines for interconnecting layers or devices. However, it is very important to enhance the electrical characteristic by reducing the electrical resistivity of micro via interconnection line because it affects the reliability of packaging. In this paper, Micro vias were patterned with a diameter from 10 to 100 um by increasing the step of 10 um and 100 um height and were fabricated by micromachining technology to investigate the electrical characteristic of micro via interconnection lines. These micro vias were filled with copper by electroplating process with appling pulse current mode. And the electrical characteristics of micro via interconnection lines were measured. The measured value of electrical resistivity shows with a range from 20 to $26\;m{\Omega}$. This value from micro via interconnection lines fabricated by pulse current mode electroplating process shows better result than the resistivity from than micro via interconnection lines fabricated by DC mode ($31\;m{\Omega}$).

• 한국전기전자재료학회논문지
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• 제25권7호
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• pp.496-499
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• 2012

Modified structure of copper pillar bump which has trapezoidal cross section on the top region is suggested with simulation results and concept of fabrication process. Due to the large surface area of joint region between bump and solder in suggested structure, electro-migration effect can be reduced. Reduction of electro-migration is related with current density and joule heating in bump and investigated with finite element methods with variation of dimensional parameters. Mechanical characteristics are also investigated with comparing modified copper pillar bump and conventional copper pillar bump.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 The IMAPS-Korea Workshop 2001 Emerging Technology on packaging
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• pp.95-99
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• 2001

Cu is considered as a promising alternative interconnection material to Al-based interconnection materials in Si-based integrated circuits due to its low resistivity and superior resistance to the electromigration. New humping and UBM material systems for solder flip chip interconnection of Cu pads were investigated using electroless-plated copper (E-Cu) and electroless-plated nickel (E-Ni) plating methods as low cost alternatives. Optimally designed E-Ni/E-Cu UBM bilayer material system can be used not only as UBMs for solder bumps but also as bump itself. Electroless-plated E-Ni/E-Cu bumps assembled using anisotropic conductive adhesives on an organic substrate is successfully demonstrated and characterized in this study

• Current Optics and Photonics
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• 제7권1호
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• pp.38-46
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• 2023

Optical Fourier-domain reflectometry (OFDR) sensors have been widely used to measure distances with high resolution and speed in a noncontact state. In the electroplating process of a printed circuit board, it is critically important to monitor the copper-plating thickness, as small deviations can lead to defects, such as an open or short circuit. In this paper we employ a phase-based OFDR sensor for in situ relative distance sensing of a sample with nanometer-scale resolution, during electroplating. We also develop an optical-path difference (OPD)-regulated sensing probe that can maintain a preset distance from the sample. This function can markedly facilitate practical measurements in two aspects: Optimal distance setting for high signal-to-noise ratio OFDR sensing, and protection of a fragile probe tip via vertical evasion movement. In a sample with a centimeter-scale structure, a conventional OFDR sensor will probably either bump into the sample or practically out of the detection range of the sensing probe. To address this limitation, a novel OPD-regulated OFDR system is designed by combining the OFDR sensing probe and linear piezo motors with feedback-loop control. By using multiple OFDR sensors, it is possible to effectively monitor copper-plating thickness in situ and uniformize it at various positions.

• 한국전기전자재료학회논문지
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• 제23권12호
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• pp.919-923
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• 2010

Copper pillar tin bump (CPTB) was developed for high density chip interconnect technology. Copper pillar tin bumps that have $100{\mu}m$ pitch were introduced with fabrication process using a KM -1250 dry film photoresist (DFR), copper electroplating method and Sn electro-less plating method. Mechanical shear strength measurements were introduced to characterize the bonding process as a function of thermo-compression. Shear strength has maximum value with $330^{\circ}C$ and 500 N thenno-compression process. Through the simulation work, it was proved that when the copper pillar tin bump decreased in its size, it was largely affected by the copper oxidation.

• Korean Chemical Engineering Research
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• 제54권4호
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• pp.548-554
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• 2016

Damascene 구조를 갖는 반도체소자의 구리금속배선 식각공정에서 배선재료에 의해서 발생되는 구리 식각잔류물을 제거하기 위해 oxalic acid (OA), lactic acid (LA) 및 citric acid (CA)의 카르복시산 함유된 반수계 혼합세정액을 제조하고 특성을 분석하였다. 카르복시산은 pH에 따라 카르복실기와 구리이온들과의 다양한 복합체를 형성하며 세정특성의 변화를 준다. 카르복시산들이 함유된 각각의 세정액의 세정특성평가결과 10 wt% CA를 함유한 반수계 세정액의 식각잔류물 세정특성은 pH 2에서 7까지의 영역에서 가장 낮은 구리 식각률을 보였으며 pH 2에서 4까지 구리에 대한 구리산화물의 가장 높은 식각 선택도를 나타내었으나 pH 5에서 7 범위에서는 10 wt% LA가 함유된 세정액이 더 높은 선택도를 보였다. 따라서 표면세정효과는 pH에 따라 변화하며 적절한 카르복시산을 사용함이 요구된다. CA가 함유된 세정액의 경우에 CA 농도와 구리에 대한 구리산화물의 식각 선택도의 증가특성을 보이며 CA가 5 wt%이상 함유된 경우에는 세정 후 구리배선의 표면이 88 %이상의 금속구리로 분석되어 구리산화물로 구성된 식각 잔류물의 제거에 효과적임을 알 수 있었다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2004년도 추계 기술심포지움 초록집
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• pp.27-27
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• 2004