• Journal of Welding and Joining
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• v.32 no.3
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• pp.53-59
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• 2014

The mechanical stability of solder joints in electronic devices with Sn-Ag-Cu is a continuous issue since the material was applied to the industry. Various shock test methods were developed and standardized tests are used in the industry worldwide. Although it is applied for several years, the detailed mechanism of the shock induced failure mechanism is still under investigation. In this study, the effect of external temperature was observed on large Flip-chip BGA components. The weight and size of the large package produced a high strain region near the corner of the component and thus show full fracture at around 200G level shock input. The shock performance at elevated temperature, at $100^{\circ}C$ showed degradation based on board pad designs. The failure mode and potential failure mechanisms are discussed.

• Journal of the Korean institute of surface engineering
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• v.29 no.6
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• pp.709-713
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• 1996

Mechanical solderless chip packaging with small gold bumps or metal balls has increased in the electronic devices. The preparation of conductive particles (5~7 $\mu\textrm{m}$ diamiter) by electroless nickel plating have been investigated. Generally, batch type electroless plating is applied to provide conductivity on the nonconductors. Since the surface areas of particles are much larger than the bulk substrate, accordingly the electroless plating bath becomes unstable. Thus, we applied the continuous dropping method for the preparation of conductive particles. The uniform coverage of deposited nickel on the particles was obtained by using ammonium acetate as a complexing agent, and surface coverage is further improved without coagulation of particles by the surface active agent treatment before enter the plating bath.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.664-665
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• 2013

This paper present a method of constructing the multimedia processor architecture. The proposed multimedia processor architecture be able to handle each text, sound, and video in one chip. Also it have interactive function that is a characteristics of multimedia. Specially, the proposed multimedia processor be able to addressing nodes in memory map without software, and it is completely reconfigurable depend on data. Also it as able to process time and space common that have synchronous/asynchronous and it is able to protect continuous and dynamic media bus collision, and local and overall common memory structure. The proposed multimedia processor architecture apply to virtual reality and mixed reality.

• Proceedings of the KIEE Conference
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• 2009.04b
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• pp.152-155
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• 2009

In high power application, PFC(Power Factor Correction) pre-regulators are generally required. PFC pre-regulators could achieve unity power factor, reduce line input current harmonics and utilize full line power. Interleaving PFC converters could reduce input ripple current, output capacitor ripple current and inductor size. With this closed loop interleaving method, both two phase converters are working at the boundary between continuous and discontinuous mode and accurate 180 degree phase shift is achieved. Implementation of this strategy could be easily integrated to the control chip. Finally, experimental results of a two-phase interleaved boost PFC are presented to verify the discussed features.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.8
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• pp.1464-1469
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• 2008

A CMOS Gm-C filter with variable cutoff frequency applicable for using in the direct conversion receiver is designed. The designed filter comprises the CMOS differential transconductors, and the gm of the transconductor is controlled by the bias voltage. This configuration can compensate variant of the cutoff frequency which could be generated by external noises, and also be used in multiband receiver. As a results of HSPICE simulation, the control range of the cutoff frequency is $1.5MHz{\sim}3.5MHz$ and the gain control range is $-2.8dB{\sim}2.6dB$. The layout of the designed 5th-order Elliptic low-pass filter is performed to fabricate a chip using $2.5V-0.25{\mu}m$ CMOS processing parameter.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.920-923
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• 2003

An wearable electrocardiogram (ECG) monitoring system is a widely used non-invasive diagnostic tool for ambulatory patient who may be at risk from latent life-threatening cardiac abnormalities. In this paper, we have a portable ECG monitoring system with conductive fiber which was characterized by the small-size and the low power consumption. The system consists of conductive fibers, one-chip microcontroller, ECG preprocessing circuit, and monitoring software to be able to record and analyze in PC. ECG preprocessing circuit is made of pre-amplifier with gain of 10, band-pass filter with bandwidth of 0.5-120Hz and 2.5V offset circuit for A/D conversion. ECG signals obtained by sensor are included with corrupted noises such as a baseline wandering, 60 Hz power noise and interference noise by body movement. For cancellation corrupted noises in signals obtained by conductive fiber, we used the wavelet decomposition of wavelet transforms in MATLAB toolbox.

• Journal of the Korea Society of Computer and Information
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• v.5 no.3
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• pp.76-83
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• 2000

The continuous time signal system by development of CMOS technology have been receiving consideration attention. In this paper, Low pass filter using new CMOS floating resistor have been designed with cut off frequency for speech signal Processing. Especially a new floating resistor consisting entirely of CMOS devices in saturation has been developed. Linearity within $\pm$0.04% is achieved through nonlinearity via current mirrors over an applied range of $\pm$1V The frequency response exceeds 10MHz, and the resistors are expected to be useful in implementing integrated circuit active RC filters. The low pass filter designed using this method has simpler structure than switched capacitofilter. So reduce the chip area. The characteristics of the designed low pass filter using this method are simulated by pspice program.

• International journal of advanced smart convergence
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• v.13 no.2
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• pp.25-34
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• 2024

The paper investigates how the semiconductor and electric vehicle industries are addressing safety and security concerns in the era of autonomous driving, emphasizing the prioritization of safety over security for market competitiveness. Collaboration between these sectors is deemed essential for maintaining competitiveness and value. The research suggests solutions such as advanced autonomous driving technologies and enhanced battery safety measures, with the integration of AI chips playing a pivotal role. However, challenges persist, including the limitations of big data and potential errors in semiconductor-related issues. Legacy automotive manufacturers are transitioning towards software-driven cars, leveraging artificial intelligence to mitigate risks associated with safety and security. Conflicting safety expectations and security concerns can lead to accidents, underscoring the continuous need for safety improvements. We analyzed the expansion of electric vehicles as a means to enhance safety within a framework of converging security concerns, with AI chips being instrumental in this process. Ultimately, the paper advocates for informed safety and security decisions to drive technological advancements in electric vehicles, ensuring significant strides in safety innovation.

• Journal of IKEEE
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• v.14 no.1
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• pp.33-39
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• 2010

In this paper, a 5Gb/s receiver with an adaptive equalizer for serial link interfaces is proposed. For effective gain control, a least-mean-square (LMS) algorithm was implemented with two internal signals of slicers instead of output node of an equalizing filter. The scheme does not affect on a bandwidth of the equalizing filter. It also can be implemented without passive filter and it saves chip area and power consumption since two internal signals of slicers have a similar DC magnitude. The proposed adaptive equalizer can compensate up to 25dB and operate in various environments, which are 15m shield-twisted pair (STP) cable for DisplayPort and FR-4 traces for backplane. This work is implemented in $0.18-{\mu}m$ 1-poly 4-metal CMOS technology and occupies $200{\times}300{\mu}m^2$. Measurement results show only 6mW small power consumption and 2Gbps operating range with fabricated chip. The equalizer is expected to satisfy up to 5Gbps operating range if stable varactor(RF) is supported by foundry process.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2008.11a
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• pp.18-18
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• 2008

3차원 패키징 System In Package (SIP)구조에서 Chip to Chip 단위 Interconnection 역할을 하는 Through Silicon Via(TSV)를 형성하기 위하여 Pulsating RF bias가 장착된 Inductively Coupled Plasma Etcher 장비를 이용하였다. 이 Pulsating 플라즈마 공정 방법은 주기적인 펄스($50{\sim}500Hz$)와 듀티($20{\sim}99%$) cycle 조절이 가능하며, 플라즈마 에칭특성에 영향을 주는 플라즈마즈마 발생 On/Off타임을 조절할 수 있다. 예를 들면, 플라즈마 발생 Off일 경우에는 이온(SFx+, O+)과 래디컬(SF*, F*, O*)의 농도 및 활성도를 급격하게 줄이는 효과를 얻을 수가 있는데, 이러한 효과는 식각 에칭시, 이온폭격의 손상을 급격하게 줄일 수 있으며, 실리콘 표면과 래디컬의 화학적 반응을 조절하여 에칭 측벽 식각 보호막 (SiOxFy : Silicon- Oxy- Fluoride)을 형성하는데 영향을 미친다. 그리고, TSV 형성에 있어서 큰 문제점으로 지적되고 있는 언더컷과 수평에칭 (Horizontal etching)을 개선하기 위한 방법으로, Black-Siphenomenon을 이번 실험에 적용하였다. 이 Black-Si phenomenon은 Bare Si샘플을 이용하여, 언더컷(Undercut) 및 수평 에칭 (Horizontal etching)이 최소화 되는 공정 조건을 간편하게 평가 할 수 있는 방법으로써, 에칭 조건 및 비율을 최적화하는 데 효율적이었다. 결과적으로, Pulsating RF bias가 장착된 Inductively Coupled Plasma Etcher 장비를 이용한 에칭실험은 펄스 주파수($50{\sim}500Hz$)와 듀티($20{\sim}99%$) cycle 조절이 가능하여, 이온(SFx+, O+)과 래디컬(SF*, F*, O*)의 농도와 활성화를 조절 하는데 효과적이었으며, Through Silicon Via (TSV)를 형성 하는데 있어서 Black-Si phenomenon 적용은 기존의 Continuous 플라즈마 식각 결과보다 향상된 에칭 조건 및 에칭 프로파일 결과를 얻는데 효과적이었다.