• IE interfaces
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• v.10 no.1
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• pp.57-65
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• 1997

Less researches on AGV(Automated Guided Vehicle) path configurations have been conducted so far while more studies have been placed in determining AGV guide path directions and pick-up/drop-off station locations, and routing/dispatching/scheduling strategies. In practice plenty of concerns fall in preventing deadlock and simplifying AGV system control through an appropriate AGV path configuration. In order to meet those requirements, a new AGV path configuration, inter-loop stocker type is introduced here. The stocker serves as relaying material between loops as well as stocking material. Automated material handling systems using AGVs play an important role in semiconductor industry including TFT LCD and memory/non-memory chip. A practical example of implementing the inter-loop stocker concept successfully in the TFT LCD fab is presented in this paper.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10b
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• pp.1327-1331
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• 1990

A new dual loop controller using color LCD bar graphs with LED back lights has been developed. An optional memory card is used to load or save the controller configuration, which may be a preprogrammed standard package or a user-programmed configuration, in addition to the built-in functions ready for user selection. The bar-graph display is selectable for single-loop or dual-loop use. A high grade of self-tuning functions using a modeling technique is built-in as standard. The controller can accommodate optional plug-in modules for thermocouples, communication, etc. All the options are fully field upgradable.

• Korean Institute of Interior Design Journal
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• v.21 no.2
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• pp.46-55
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• 2012

This study aims to analyze the design concepts of Libeskind's Jewish museums through their comparisons for figuring out his design intentions and characteristics in the realization process. Libeskind's realized four Jewish museums are chosen for this study. For more concrete study, their extracting and application process are also reviewed. The comparison of his museum designs can be good examples in that they show different design approaches on the same architectural type, Jewish museum, to tell their something in common from differences. He could realize his architectural thoughts and configuration methods made by experimental drawings for the first time as real buildings through a series of Jewish museum projects. The commonness of Libeskind's Jewish museums lie on their sharing design concept of Jewish 'history and memory', especially Holocaust, and realized as in contrast to surroundings and 'labyrinth' of spatial configuration to maximize spectator's experiences. As Libeskind regards museum architecture as a carrier of 'time and place', he tried to reflect surrounding context including places, cities, persons and events about museum programs. As a result, unprecedented museums which are not related to traditional museum systems about circulation and spatial configuration are suggested for users to experience Jewish life and history through architecture.

• Nuclear Engineering and Technology
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• v.49 no.8
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• pp.1589-1599
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• 2017

Field programmable gate arrays (FPGAs) are getting more attention in safety-related and safety-critical application development of nuclear power plant instrumentation and control systems. The high logic density and advancements in architectural features make static random access memory (SRAM)-based FPGAs suitable for complex design implementations. Devices deployed in the nuclear environment face radiation particle strike that causes transient and permanent failures. The major reasons for failures are total ionization dose effects, displacement damage dose effects, and single event effects. Different from the case of space applications, soft errors are the major concern in terrestrial applications. In this article, a review of radiation effects on FPGAs is presented, especially soft errors in SRAM-based FPGAs. Single event upset (SEU) shows a high probability of error in the dependable application development in FPGAs. This survey covers the main sources of radiation and its effects on FPGAs, with emphasis on SEUs as well as on the measurement of radiation upset sensitivity and irradiation experimental results at various facilities. This article also presents a comparison between the major SEU mitigation techniques in the configuration memory and user logics of SRAM-based FPGAs.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.2
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• pp.75-84
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• 2005

This research is to design a high performance NAND-type flash memory package with a smart buffer cache that enhances the exploitation of spatial and temporal locality. The proposed buffer structure in a NAND flash memory package, called as a smart buffer cache, consists of three parts, i.e., a fully-associative victim buffer with a small block size, a fully-associative spatial buffer with a large block size, and a dynamic fetching unit. This new NAND-type flash memory package can achieve dramatically high performance and low power consumption comparing with any conventional NAND-type flash memory. Our results show that the NAND flash memory package with a smart buffer cache can reduce the miss ratio by around 70% and the average memory access time by around 67%, over the conventional NAND flash memory configuration. Also, the average miss ratio and average memory access time of the package module with smart buffer for a given buffer space (e.g., 3KB) can achieve better performance than package modules with a conventional direct-mapped buffer with eight times(e.g., 32KB) as much space and a fully-associative configuration with twice as much space(e.g., 8KB)

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.105-111
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• 2013

We have developed an analog associative memory implemented with an analog array which has linear writing and erasing characteristics. The associative memory adopts a winner-take-all strategy. The operation for reading in the memory is executed with an absolute differencing circuit and a winner-take-all (WTA) circuit suitable for a nearest-match function of a content-addressable memory. We also present a system architecture that enables highly-paralleled fast writing and quick readout as well as high integration density. A multiple memory cell configuration is also presented for achieving higher integration density, quick readout, and fast writing. The system technology presented here is ideal for a real time recognition system. We simulate the function of the mechanism by menas of Hspice with $1.2{\mu}$ double poly CMOS parameters of MOSIS fabrication process.

• The KIPS Transactions:PartD
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• v.13D no.3 s.106
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• pp.377-382
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• 2006

Advantageous features of flash memory are stimulating its exploitation in mobile and ubiquitous related devices. The hardware characteristics of flash memory however place restrictions upon this current trend. In this paper, a cleaning policy for flash memory is proposed in order to decrease the necessary penally for recycling of memory minimizing the degradation of performance at the same time. The proposed cleaning algorithm is based on partitioning of candidate memory regions, to be reclaimed as free, into a number of groups. In addition, in order to improve the balanced utilization of the entire flash memory space in terms of 'wearing-out', a free segment selection algorithm is discussed. The impact of the proposed algorithms is evaluated through a number of experiments. Moreover, the composition of the optimal configuration featuring the proposed methods is tested through experiments.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5465-5470
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• 2012

FPGA(Field Programmable Gate Array) devices are widely used due to their merits in circuit development time, and development cost. Among various FPGA technologies, SRAM-based FPGAs have large cell capacity so that they are attractive for complex circuit design and their reconfigurability. However, they are weak in space environment where radiation energy particles cause Single Event Upset(SEU). In this paper, we designed a controller supervising SRAM-based FPGA to protect configuration memory inside. The controller is implemented on an Anti-Fusing FPGA. Radiation test was performed on the implemented computer board and the result show that our controller provides better SEU-resilience than TMR-only system.

• Journal of the Optical Society of Korea
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• v.14 no.3
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• pp.260-265
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• 2010

This paper proposes a transflective configuration of the dual operating mode liquid crystal display, which has transmissive dynamic and reflective memory parts in its pixel. By employing a wideband structure and optimizing the cell-gap of the liquid crystal layer, the reflective memory part shows a very low reflectance in the dark state, good dispersion properties for the entire visible range, as well as high reflectance in the bright state. The transmissive dynamic part is designed to have the same cell-gap and rubbing direction as those of the reflective part. The driving voltage of the dynamic part and transmittance of the bright state can also be controlled by using compensation film with a positive a-plate, which can compensate the reflective part. Experimental results in the memory part operation demonstrate that the contrast ratio is over 50:1 and the reflectance in the dark state is reduced to 56% on average of that of the conventional dual mode configuration for the entire visible range. The contrast ratio of the dynamic part is 300:1.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.11
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• pp.3619-3637
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• 2022

Big data analytics offers endless opportunities for operational enhancement by extracting valuable insights from complex voluminous data. Hadoop is a comprehensive technological suite which offers solutions for the large scale storage and computing needs of Big data. The performance of Hadoop is closely tied with its configuration settings which depends on the cluster capacity and the application profile. Since Hadoop has over 190 configuration parameters, tuning them to gain optimal application performance is a daunting challenge. Our approach is to extract a subset of impactful parameters from which the performance enhancing sub-optimal configuration is then narrowed down. This paper presents a statistical model to analyze the significance of the effect of Hadoop parameters on a variety of performance metrics. Our model decomposes the total observed performance variation and ascribes them to the main parameters, their interaction effects and noise factors. The method clearly segregates impactful parameters from the rest. The configuration setting determined by our methodology has reduced the Job completion time by 22%, resource utilization in terms of memory and CPU by 15% and 12% respectively, the number of killed Maps by 50% and Disk spillage by 23%. The proposed technique can be leveraged to ease the configuration tuning task of any Hadoop cluster despite the differences in the underlying infrastructure and the application running on it.