• Proceedings of the Optical Society of Korea Conference
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• 1998.08a
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• pp.170-171
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• 1998

Here are proposed the tunable laser for optical memory which uses the acousto-optic deflector. This laser includes the acousto-optic deflector in the Littrow mount configuration so that we may control the beam deflection by means of the induced RF. Consequently, we can achieve the higher speed and accuracy to compare with the Littrow monut configuration only.

• Journal of IKEEE
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• v.17 no.2
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• pp.168-175
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• 2013

The delay times due to the propagating of data on PCB depend on the shape and length of interconnection lines when memory controllers and high speed memories are soldered on the PCB. The dependency on the placement and routing on the PCB requires redesign of I/O logic or reconfiguration of the memory controller after the delay time is measured if the controller is programmable. In this paper, we propose architecture of configuring logic for the delay time estimation by writing and reading test patterns while initializing the memories. The configuration logic writes test patterns to the memory and reads them by changing timing until the correct patterns are read. The timing information is stored and the configuration logic configures the memory controller at the end of initialization. The proposed method enables easy design of systems using PCB by solving the problem of the mismatching caused by the variation of placement and routing of components including memories and memory controllers. The proposed method can be applied to high speed SRAM, DRAM, and flash memory.

• Broadcasting and Media Magazine
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• v.7 no.3
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• pp.75-82
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• 2002

In this report, the complexity analysis of the JVT(Joint Video Team) codec, which has jointly developed the next video coding standard, is performed. Three types of configurations in terms of coding efficiency are set and the analysis of the memory band width and computation time for each configuration is performed. ATOMIUM complexity analysis tool is used for both the memory access statistics and computation time calculation of JVT codec. Also the complexity of each video coding tool in the encoder and decoder is shown in relative complexity.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.2
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• pp.178-184
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• 2004

In this paper, we designed an image processing system for the high speed line-scan camera which adopts the new memory model we proposed. As a resolution and a data rate of the line-scan camera are becoming higher, the faster image processing systems are needed. But many conventional systems are not sufficient to process the image data from the line-scan camera during a very short time. We designed the memory controller which eliminates the time for transferring image data from the line-scan camera to the main memory with high-speed SRAM and has a dual-port configuration therefore the DSP can access the main memory even though the memory controller are writing the image data. The memory controller is implemented by VHDL and Xilinx SPARTAN-IIE FPGA.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.596-599
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• 1997

In this study, the flow control system with shape memory alloy in jet engine inlet was suggested to adjust the shock boundary layer interact~on for supersonic flight system. It consisted of the flap with shape memory alloy, spar with steel, and fixing device with aluminum alloy. The advantages of itself are a simple configuration, a passive air circulation by using the flap deflection due to pressure difference, and no need to be required the auxiliary devices. Finite element analysis was conducted to predict the thenno-mechanical behavlor of the flap system with shape memory alloy. The user-defined subroutine UMAT was implemented with ABAQUS to accon~modate the thermo-mechanical constitutive relation of shape memory alloy.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.1
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• pp.69-77
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• 2021

The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.

• Journal of Information Processing Systems
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• v.14 no.2
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• pp.499-509
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• 2018

Recently, hybrid transactional memory (HyTM) has gained much interest from researchers because it combines the advantages of hardware transactional memory (HTM) and software transactional memory (STM). To provide the concurrency control of transactions, the existing HyTM-based studies use a bloom filter. However, they fail to overcome the typical false positive errors of a bloom filter. Though the existing studies use a global lock, the efficiency of global lock-based memory allocation is significantly low in multi-core environment. In this paper, we propose an efficient hybrid transactional memory scheme using near-optimal retry computation and sophisticated memory management in order to efficiently process transactions in multi-core environment. First, we propose a near-optimal retry computation algorithm that provides an efficient HTM configuration using machine learning algorithms, according to the characteristic of a given workload. Second, we provide an efficient concurrency control for transactions in different environments by using a sophisticated bloom filter. Third, we propose a memory management scheme being optimized for the CPU cache line, in order to provide a fast transaction processing. Finally, it is shown from our performance evaluation that our HyTM scheme achieves up to 2.5 times better performance by using the Stanford transactional applications for multi-processing (STAMP) benchmarks than the state-of-the-art algorithms.

• Electronics and Telecommunications Trends
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• v.39 no.1
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• pp.62-73
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• 2024

Artificial intelligence relies on data-driven analysis, and the data processing performance strongly depends on factors such as memory capacity, bandwidth, and latency. Fast and large-capacity memory can be achieved by composing numerous high-performance memory units connected via high-performance interconnects, such as Compute Express Link (CXL). CXL is designed to enable efficient communication between central processing units, memory, accelerators, storage, and other computing resources. By adopting CXL, a composable computing architecture can be implemented, enabling flexible server resource configuration using a pool of computing resources. Thus, manufacturers are actively developing hardware and software solutions to support CXL. We present a survey of the latest software for CXL memory utilization and the most recent CXL memory emulation software. The former supports efficient use of CXL memory, and the latter offers a development environment that allows developers to optimize their software for the hardware architecture before commercial release of CXL memory devices. Furthermore, we review key technologies for improving the performance of both the CXL memory pool and CXL-based composable computing architecture along with various use cases.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.1-9
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• 2012

Quantum-Inspired Evolutionary Algorithm(QEA) contains sufficient data-level parallelism to be naturally accelerated on GPUs. For an efficient reduction of execution time, however, careful task-mapping should be done to properly reflect the characteristics of CPU and GPU. Furthermore, when deciding which part of the application should run on GPU, we need to consider the data transfer between CPU and GPU memory spaces as well as the data-level parallelism. In addition, the usage of zero-copy host memory, proper choice of the execution configuration, and thread organization considering memory coalescing is important to further reduce the execution time. With all these techniques, we could run QEA 3.69 times faster on average in comparison with the multi-threading CPU for the case of 0-1 knapsack problem with 30,000 items.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.904-906
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• 2009

Organic field-effect transistor (OFET) memory is an emerging device for its potential to realize light-weight, low cost flexible charge storage media. Here we report on a solution-processed poly[9,9-dioctylfluorenyl-2,7-diyl]-co-(bithiophene)] (F8T2) nano floating-gate memory (NFGM) with top-gate/bottom-contact device configuration. A reversible shift in the threshold voltage ($V_{Th}$) and the reliable memory characteristics were achieved by incorporation of thin Au nanoparticles (NPs) as charge storage sites for negative electrons at the interface between polystyrene and cross-linked poly(4-vinylphenol).