• Journal of Biosystems Engineering
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• v.13 no.3
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• pp.59-70
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• 1988

A computer simulation model for rice circulating concurrent-flow dryer was developed and verified by conduction a series of pilot-scale experiment. The effects of design parameter and operating conditions on dryer performance were analyzed by using simulation. The results indicated that the developed model was found suitable for analyzing operating characteristics. The other results from simulation also showed that; 1) an increse in the initial moisture content resulted in an increase in the drying rate and a reduction in the grain temperature and total energy requirements. 2) an increase in the drying air temperature resulted in an increase in the drying rate and grain temperature. 3) an increase in air flow rate resulted in an radical increase in drying rate, fan power requirements and total energy requirements but an radical decrease in final head rice yield. 4) an increase in the bed depth resulted in an increase in fan power requirements and a lowering of the final head rice yield.

• Journal of Biosystems Engineering
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• v.31 no.4 s.117
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• pp.349-354
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• 2006

This study was performed to evaluate the performances for a concurrent flow rice dryer of pilot scale with devices for circulating rice. The pilot scale dryer with the capacity of 700 kg was developed to obtain design informations for the development of actual scale dryer of holding capacity of 10 tons. Three drying tests were conducted at two temperature levels of $100^{\circ}C\;and\;120^{\circ}C$, and two air flow rates levels of $28.5cmm/m^2\;and\;57.1cmm/m^2$. Drying conditions for Test-1, Test-2 and Test-3 were $100^{\circ}C\;-28.5cmm/m^2,\;120^{\circ}C-28.5cmm/m^2\;and\;120^{\circ}-57.1cmm/m^2}$ respectively. Drying rates were 0.73%(w.b./h) for Test-1, 0.90%(w.b./h) for Test-2 and 1.46%(w.b./h) for Test-3. The crack ratios of brown rice after drying ranged from 2.4% to 8.4%, and increased with the increase of drying rate and airflow rate. The energy consumptions were from 6,225 kJ/kg to 6,993 kJ/kg which was higher than that of conventional cross-flow rice circulating type dryer used in Korea. This results were due to the lower ambient air temperatures of $4.5^{\circ}C\;to\;13.4^{\circ}C$ during drying tests.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.7
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• pp.2354-2370
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• 2015

The advantages of employing SCTP-based Concurrent Multipath Transfer (CMT) have been demonstrated to be very useful for data delivery over multi-homed wireless networks. However, there is still significant ongoing work addressing some remaining limitations and challenges. The most important concern when applying CMT to data delivery is related to handling packet reordering and buffer blocking. Another concern on this topic is that current sender-based CMT solutions seldom consider balancing the overhead and sharing the load between the sender and receiver. This paper proposes a novel Receiver-driven Cooperation-based Concurrent Multipath Transfer solution (CMT-Rev) with the following aims: (i) to balance overhead and share load between the sender and receiver, by moving some functions including congestion and flow control from the sender onto receiver; (ii) to mitigate the data reordering and buffer blocking problems, by using an adaptive receiver-cooperative path aggregation model, (iii) to adaptively transmit packets over multiple paths according to their receiver-inspired sending rate values, by employing a new receiver-aware data distribution scheduler. Simulation results show that CMT-Rev outperforms the existing CMT solutions in terms of data delivery performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.91-102
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• 2005

Recently, concurrent error detection for the processor becomes important. But it imposes too much overhead to adopt concurrent error detection capability on the system. In this paper, a new approach to resolve the problems of concurrent error detection is proposed. A loop detection scheme is introduced to reduce the repetitive loop iteration and memory access. To reduce the memory overheat an offset to calculate the target address of branching node is proposed. Performance evaluation shows that the new architecture has lower memory overhead and frequency of memory access than previous works. In addition, the new architecture provides the same error coverage and requires nearly constant memory size regardless of the size of the application program. Consequently, the proposed architecture can be used as an cost effective method to detect control flow errors in the commercial on the shelf products.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.987-992
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• 2005

Manufacturing companies should perform process planning and its evaluation concurrently with new product developments so that they can be highly competitive in the modern market. Process planners should make decisions in the manner of concurrent and collaborative engineering in order to reduce the manufacturing preparation time and cost when developing new products. Automated generation of analysis models from the integrated database, which contains process and material information, reduces time to prepare analyses and makes the models reliable. In this research, we developed a web-based system for concurrent and collaborative system for production flow analysis, using web, database, and simulation technology. An integrated database is designed to automatically generate analysis models from process and material plans without reworking the data. This system enables process planners to evaluate their decision fast and share their opinions with others easily. With this system, it is possible to save time and cost for assembly process and material planning, and reliability of process plans can be improved

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.6
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• pp.2870-2888
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• 2017

Recent studies have shown that the flow table size of hardware SDN switch cannot match the number of concurrent flows. Combined SDN Forwarding Element (CFE), which comprises several software switches and a hardware switch, becomes an alternative approach to tackle this problem. Due to the limited capacity of software switch, the way to route concurrent flows in CFE can largely affect the maximum delay that a flow suffers at CFE. As delay-guarantee is a nontrivial task for network providers with the increasing number of delay-sensitive applications, we propose an analytical model of CFE to evaluate a rules placement solution first. Next, we formulate the problem of Rules Placement with delay guarantee in CFE (RPCFE), and present the genetic-based rules placement (GARP) algorithm to solve the RPCFE problem. Further, we validate the analytical model of CFE through simulations in NS-3 and compare the performance of GARP with three benchmark algorithms.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.11a
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• pp.234-237
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• 2014

This paper provides insights into the sFlow monitoring system of OF@KREONET. OF@KREONET is software defined network (SDN) testbed adapted by KREONET (Korea Research Environment Open NETwork). OF@KREONET uses SDN-based network virtualization to slice the network among multiple concurrent experimenter. Flow Monitoring of OF@KREONET using sFlow. sFlow and OpenFlow can be used to provide an integrated flow monitoring system where OpenFlow controller can be used to define flows to be monitored by sFlow. OF@KREONET flow monitoring system supports monitoring of per slice FlowSpace. An Experimental can monitor his/her own FlowSpace while network administrator can monitor all spaces.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.5
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• pp.149-157
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• 1994

This paper Presents an algorithm for synthesis of sequential statements described at RT level VHDL. The proposed algorithm transforms sequential statements in VHDL into data-flow description consisting of concurrent statements by local and global dependency analysis and output dependency elimination. Transformation into concurrent statements makes it possible to reduce the cost of the synthesized hardwares, thus to get optimal synthesis results that will befit the designer 's intention. This algorithm has been implemented on VSYN and experimental results show that more compact gate-level hardwares are generated compared with Power View system from ViewLogic and Design Analyzer from Synopsys.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10b
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• pp.463-465
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• 1998

COncurrent Design Approach for Real-Time System(이하 COSATRS) 방법론은 Gomaa가 제안한 실시간 설계 방법론으로서 Real-Time Structured Analysis(이하 RTSA)또는 Concurrent Object-Based Real-Time Analysis(이하 COBRA)방법론을 이용하여 Control and Data Flow Diagram(이하 C&DFD)를 구성하고 이것에 병렬 태스크 구조화 지침, 정보 은닉 모듈 구조화 지침을 적용하여 Task Architecture Diagram (이하 TDA), Information Hiding Module(이하 IHM)을 구성하고 나서 이 둘을 결합하여 Software Architecture Diagram(이하 SAD)를 구성하게 된다. 본 논문에서는 CODARTS 방법론의 적용과정을 테이블을 구성하여 적용함으로써 실시간 S/W 설계 지원 시스템을 설계하였다.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.34 no.8
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• pp.301-307
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• 1985

The first four generations of computers are all based on a single basic design: the Von Neuman Processor, which is sequential and does one operation at a time. Efforts to develop concurrent or parallel computers have been carried on for many years. Data flow approach is significant in these efforts to make high speed parallel machines and expected a great deal of parallelism. In this paper we propose a preliminary data Flow Machine Model operating asynchronously on the base of Node Labelling. We introduce a concept of Node Labeling for this purpose which is relevant to the Data dependency and Parallelism. And we explain how the Node Tokens are fired in the proposed system.