• Title/Summary/Keyword: Computing time-delay

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A Two-Step Call Admission Control Scheme using Priority Queue in Cellular Networks (셀룰러 이동망에서의 우선순위 큐 기반의 2단계 호 수락 제어 기법)

  • 김명일;김성조
    • Journal of KIISE:Information Networking
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    • v.30 no.4
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    • pp.461-473
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    • 2003
  • Multimedia applications are much more sensitive to QoS(Quality of Service) than text based ones due to their data continuity. In order to provide a fast moving MH(Mobil Host) using multimedia application with a consistent QoS,an efficient call admission mechanism is in need. This paper proposes the 2SCA(2-Step Call Admission) scheme based on cal admission scheme using pripority to guarantee the consistent QoS for mobile multimedia applications. A calls of MH are classified new calls, hand-off calls, and QoS upgrading calls. The 2SCA is composed of the basic call admission and advanced call admission; the former determines the call admission based on bandwidth available in each cell and the latter determines the call admission by applying DTT(Delay Tolerance Time), PQeueu(Priority Queue), and UpQueue(Upgrade Queue) algorithm according to the type of each call blocked at the basic call admission stage. In order to evaluate the performance of our mechanism, we measure the metrics such as the dropping probability of new calls, dropping probability of hand-off calls, and bandwidth utilization. The result shows that the performance of our mechanism is superior to that of existing mechanisms such as CSP(Complete Sharing Policy), GCP(Guard Channel Policy) and AGCP(Adaptive Guard Channel Policy).

Multi-Hop Vehicular Cloud Construction and Resource Allocation in VANETs (VANET 망에서 다중 홉 클라우드 형성 및 리소스 할당)

  • Choi, Hyunseok;Nam, Youngju;Lee, Euisin
    • KIPS Transactions on Computer and Communication Systems
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    • v.8 no.11
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    • pp.263-270
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    • 2019
  • Vehicular cloud computing is a new emerging technology that can provide drivers with cloud services to enable various vehicular applications. A vehicular cloud is defined as a set of vehicles that share their own resources. Vehicles should collaborate with each other to construct vehicular clouds through vehicle-to-vehicle communications. Since collaborating vehicles to construct the vehicular cloud have different speeds, directions and locations respectively, the vehicular cloud is constructed in multi-hop communication range. Due to intermittent wireless connectivity and low density of vehicles with the limited resources, the construction of vehicular cloud with multi-hop communications has become challenging in vehicular environments in terms of the service success ratio, the service delay, and the transmitted packet number. Thus, we propose a multi-hop vehicular cloud construction protocol that increases the service success ratio and decreases the service delay and the transmitted packet number. The proposed protocol uses a connection time-based intermediate vehicle selection scheme to reduce the cloud failure probability of multi-hop vehicular cloud. Simulation results conducted in various environments verify that the proposed protocol achieves better performance than the existing protocol.

The Mirror-based real-time dynamic projection mapping design and dynamic object detection system research (미러 방식의 실시간 동적 프로젝션 매핑 설계 및 동적 사물 검출 시스템 연구)

  • Soe-Young Ahn;Bum-Suk Seo;Sung Dae Hong
    • Journal of Internet of Things and Convergence
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    • v.10 no.2
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    • pp.85-91
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    • 2024
  • In this paper, we studied projection mapping, which is being utilized as a digital canvas beyond space and time for theme parks, mega events, and exhibition performances. Since the existing projection technology used for fixed objects has the limitation that it is difficult to map moving objects in terms of utilization, it is urgent to develop a technology that can track and map moving objects and a real-time dynamic projection mapping system based on dynamically moving objects so that it can respond to various markets such as performances, exhibitions, and theme parks. In this paper, we propose a system that can track real-time objects in real time and eliminate the delay phenomenon by developing hardware and performing high-speed image processing. Specifically, we develop a real-time object image analysis and projection focusing control unit, an integrated operating system for a real-time object tracking system, and an image processing library for projection mapping. This research is expected to have a wide range of applications in the technology-intensive industry that utilizes real-time vision machine-based detection technology, as well as in the industry where cutting-edge science and technology are converged and produced.

Service Curve Allocation Schemes for High Network Utilization with a Constant Deadline Computation Cost (상수의 데드라인 계산 비용으로 높은 네트웍 유용도를 얻는 서비스 곡선 할당 방식)

  • 편기현;송준화;이흥규
    • Journal of KIISE:Information Networking
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    • v.30 no.4
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    • pp.535-544
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    • 2003
  • Integrated services networks should guarantee end-to-end delay bounds for real-time applications to provide high quality services. A real-time scheduler is installed on all the output ports to provide such guaranteed service. However, scheduling algorithms studied so far have problems with either network utilization or scalability. Here, network utilization indicates how many real-time sessions can be admitted. In this paper, we propose service curve allocation schemes that result in both high network utilization and scalability in a service curve algorithm. In service curve algorithm, an adopted service curve allocation scheme determines both network utilization and scalability. Contrary to the common belief, we have proved that only a part of a service curve is used to compute deadlines, not the entire curve. From this fact, we propose service curve allocation schemes that result in a constant time for computing deadlines. We through a simulation study that our proposed schemes can achieve better network utilizations than Generalized processor Sharing (GPS) algorithms including the multirate algorithm. To our knowledge, the service curve algorithm adopting our schemes can achieve the widest network utilization among existing scheduling algorithms that have the same scalability.

Development of Message Define & Management System based on Distributed Processing Environment for Naval Combat Systems (함정 전투체계를 위한 분산처리 환경 기반 메시지 정의 및 관리 시스템의 개발)

  • Lee, Juwon
    • KIISE Transactions on Computing Practices
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    • v.23 no.12
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    • pp.670-676
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    • 2017
  • Naval combat systems use real-time processing and compositing of collected information to provide the optimal combat capabilities that maximize survival and ensure mission effectiveness. The software for a combat system has dozens to thousands of components depending on the size of the system, and the communication between the components is achieved via DDS. Although the message interface of the combat system is managed through MDMS, an increase in the system size can result in problems such as the deterioration of the development efficiency. In this paper, we implement XMDMS to operate a distributed processing environment and then solve the problem of the reduction in the development efficiency caused by a load at the server. The experimental results shows that XMDMS improves the processing delay and network performance compared to MDMS.

Implementation of a LSB-First Digit-Serial Multiplier for Finite Fields GF(2m) (유한 필드 GF(2m)상에서의 LSB 우선 디지트 시리얼 곱셈기 구현)

  • Kim, Chang-Hun;Hong, Chun-Pyo;U, Jong-Jeong
    • The KIPS Transactions:PartA
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    • v.9A no.3
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    • pp.281-286
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    • 2002
  • In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication $A({\times})B$mod G ({\times})in finite fields GF $(2^m)$. If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.

Scheduling Scheme for Guaranteeing High Quality of Service in 10G EPON (10G EPON에서 높은 QoS를 보장하는 스캐줄링 방법)

  • Jun, Jae-Hyun;Jung, Min-Suk;Kim, Min-Jun;Choi, Yong-Do;Kim, Sung-Ho
    • Journal of KIISE:Computing Practices and Letters
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    • v.16 no.3
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    • pp.351-355
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    • 2010
  • The service which is required wide bandwidth is growing in these days, so building up High Speed communication system is being required. The Task Force team of IEEE 802.3ah set the EPON as a standard; next generation subscriber access network. For offering a high quality service, 10G EPON that is changed from 1Gbps uplink downlink bandwidth to 10Gbps is come up. Although Kramer had studied 10G EPON there was a QoS limitation, when load is low, End-to-End maximum delay is increased. This paper is suggesting time synch ronization method, resource reservation method, band width allocation method. We confirmed that 10EPON was able to offer quality service by the result of the OPNET.

Low-Latency Programmable Look-Up Table Routing Engine for Parallel Computers (병렬 컴퓨터를 위한 저지연 프로그램형 조견표 경로지정 엔진)

  • Chang, Nae-Hyuck
    • Journal of KIISE:Computing Practices and Letters
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    • v.6 no.2
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    • pp.244-253
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    • 2000
  • Since no single routing-switching combination performs the best under various different types of applications, a flexible network is required to support a range of polices. This paper introduces an implementation of a look-up table routing engine offering flexible routing and switching polices without performance degradation unlike those based on microprocessors. By deciding contents of look-up tables, the engine can implement wormhole routing, virtual cut-through routing, and packet switching, as well as hybrid switching, under a variety of routing algorithms. Since the routing engine has a piplelined look-up table architecture, the routing delay is as small as one flit, and thus it can overlap multiple routing actions without performance degradation in comparison with hardwired routers dedicated to a specific policy. Because four pipeline stages do not induce a hazard, expensive forwarding logic is not required. The routing engine can accommodate four physical links with a time shared cut-through bus or single link with a cross-bar switch. It is implemented using Xilinx 4000 series FPGA.

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Prefetching Methods with Vehicle's Pattern in Location-Based Services (위치기반서비스에서 차량의 패턴을 고려한 프리페칭 기법)

  • Choi, In-Seon;Kim, Joo-Hwan;Lee, Dong-Chun
    • Convergence Security Journal
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    • v.8 no.4
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    • pp.105-113
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    • 2008
  • Mobile computing environment is known to be quite difficult to provide user with a stable Quality of Service (QoS) due to vehicle mobility nature. In order to protect the inherent characteristics of wireless network such as low bandwidth and high transmission delay along with the vehicle's mobility, many works are conducted to apply caching and prefetching methods. This paper presents a novel prefetching technique which is based on owner's profile. It is the scheme with the vehicle velocity, the visit frequency and resident time of specific region for vehicle owner's past given period, and the user profile which has owner's personal inclination about a certain place. The proposed scheme shown relatively superior performance in terms of the utilization ratio of prefetched information and the failure ratio of information retrieval than the previous methods.

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Design of MSB-First Digit-Serial Multiplier for Finite Fields GF(2″) (유한 필드 $GF(2^m)$상에서의 MSB 우선 디지트 시리얼 곱셈기 설계)

  • 김창훈;한상덕;홍춘표
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.6C
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    • pp.625-631
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    • 2002
  • This paper presents a MSB-first digit-serial systolic array for computing modular multiplication of A(x)B(x) mod G(x) in finite fields $GF(2^m)$. From the MSB-first multiplication algorithm in $GF(2^m)$, we obtain a new data dependence graph and design an efficient digit-serial systolic multiplier. For circuit synthesis, we obtain VHDL code for multiplier, If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has much more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of unidirectional data flow and regularity, it shows good extension characteristics with respect to m and L.